As the RISC-V Summit Europe 2024 is underway, SiFive has announced the fourth generation of its “Essential” RISC-V CPUs (Essential Gen4) with improved power efficiency and more flexible interfaces for SoCs used in embedded devices.
The update covers 32-bit and 64-bit RISC-V cores including the U6 and U7-series 64-bit application processors, the S2, S6, and S7 64-bit real-time embedded processors, and the E2, E6, and E7 32-bit real-time embedded processors.
Essential Gen4 IP keys features:
- Up to 40% runtime power reduction
- 8x different baseline embedded 32-bit and 64-bit cores
- From 2-stage single-issue to 8-stage superscalar
- Improved L2 cache and enhanced L1 memory
- Configuration and integration options
- CPU type, profile, and options
- On-chip memories selection
- System, peripheral, and front ports
- Advanced power management and security
- Debug and trace
Software support includes embedded Linux and FreeRTOS operating systems and Eclipse-based IDE for C/C++ development.
That’s another low-quality, light-on technical details announcement from SiFive with only basic information in the press release, and although we are told we can find more details on the product page, there’s nothing of substance there either. The documentation page on the website has nothing about the SiFive Essential Gen4 CPU IP either.
It appears it was just rushed in time for RISC-V Summit Europe 2024 and possibly written for the investor class with quotes such as:
The embedded space in 2024 represents a huge ($257 billion) market opportunity, growing with an 8.3% CAGR through 2030. RISC-V and SiFive have been increasingly gaining momentum and taking share from the other ISAs. SiFive is launching the products that these customers need while also innovating at the high performance and advanced AI levels,” said Rich Wawrzyniak, Principal Analyst at The SHD Group. “It is a mistake to discount the importance of embedded products as the flexibility and software portability of RISC-V makes designing products with multiple cores—including the highest performance cores—easier, creating a clear pathway for RISC-V into the next generations of high-performance chips.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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40% !!!
Regarding the lack of details, they had a booth in the summit a couple of days ago ( https://riscv-europe.org/summit/2024/conference#demo-theatre-talk-enhancements-to-sifive-s-essential-product-line-details ) but I don’t think the foundation uploaded anything yet.
If they have more details, why not put it in the press release or product page?
I had this news under embargo since June 19. It was light on details at the time but I had expected more info at launch day.
> If they have more details, why not put it in the press release or product page?
My guess was that they just wanted to prop up their booth marketing efforts but the timing got screwy when the foundation didn’t upload in time.
But I guess another possible explanation for why the various fabless may want to keep low and withhold node and transistor count figures could a market play or even the geopolitics…
But honestly, I just don’t know.
It’s up: https://www.youtube.com/watch?v=tdu_SA2j1Fs
I watched it a 2x speed. It’s mostly a history lesson about SiFive CPUs, and then there’s a single slide about the 4th Gen series with limited information.