The PCI-SIG first unveiled the PCIe Express (PCIe) 7.0 specification at US DevCon in June 2022 with claims of bidirectional data rates of up to 512GB/s in x16 configuration, and the standard is now getting closer to the full release in 2025 with the release of the specification version 0.5.
PCIe 7.0 increases data transfer speeds to 128 GT/s per pin doubling the 64 GT/s of PCIe 6.0 and quadrupling the 32 GT/s of PCIe 5.0, delivering up to 256 GB/s in each direction in x16 configuration, excluding encoding overhead. In other words, the total maximum bandwidth of a PCIe 7.0 x1 interface (32GB/s) would be equivalent to PCIe Gen3 x16 or PCIe Gen4 x8 as shown in the table below.
PCIe 7.0 highlights:
- 128 GT/s raw bit rate and up to 512 GB/s bidirectionally via x16 configuration
- PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
- Doubles the bus frequency at the physical layer compared to PCIe 5.0 and 6.0, meaning around 30 GHz!
- Keep the 1b/1b FLIT mode encoding and the forward error correction (FEC) in PCIe 6.0
- Focuses on the channel parameters and reach
- Delivers low-latency and high-reliability targets
- Improves power efficiency
- Maintains backward compatibility with all previous generations of PCIe technology
PCIe 7.0 is probably a long way before getting into embedded systems and consumer products as it targets “data-intensive markets” such as 800Gbps Ethernet, Artificial Intelligence/Machine Learning, Hyperscale Data Centers, HPC, Quantum Computing, and the Cloud.
Anadtech says the next major step is finalization of the version 0.7 of the specification (aka the Complete Draft) which will freeze the standards’s features set. They also note that PCIe 6.0 went through 4 major drafts – 0.3, 0.5, 0.7, and 0.9 – before finally being finalized and that PCIe 7.0 might follow the same path before the final release in 2025. Even then, it will take a few years for datacenter-grade hardware to hit the shelves, and we are probably talking sometime in the 2030s before regular users can get their hands on PCIe 7.0 capable hardware.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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I really hate this marketing numbering which consists in adding both directions to provide a single value. I was seeing something wrong with these values but it took me a while to figure they were lying. With this approach, one would think that PCIe2 x16 with 16GB/s is sufficient for 100 Gbps (12.5 GB/s) but it’s not since in reality it’s 8GB/s (64 Gbps theoretical, around 63 practical with encoding, not counting the overhead of network descriptors). It’s just like low-end switches advertising the double of their bandwidth as if outgoing frames wouldn’t necessarily have entered via another port.
Regardless, we’re already seeing heating issues with PCIe5 where some vendors have less TDP margin for the CPU due to the many watts drawn by PCIe lanes. Not surprising at such rates, to be honest. I don’t know what it will be with 2x or 4x this :-/ Because we’re speaking about passing bits through shift registers at 64 GHz after all…
PCIe 6.0 switches to PAM4 and shouldn’t be harder to implement than PCIe 5.0. PCIe 7.0 is the one with the big problems.
Isn’t it about time we switched to optical interconnects? They can call it PCIo.
anandtech.com/show/19990/pcisig-forms-optical-workgroup-lighting-the-way-to-pcies-future
Not sure it would change much, there’s a point where you need to move electrical bits in transistors anyway. The real benefit of optics would be to avoid shrinking distances with increased rates. Also just thinking, but PAM4 will likely eat a lot of power, as every time transmissions turns to analog instead of digital. Ever touched a 10Gbps RJ45 transceiver and still have your finger ? 🙂