Cadence Neo NPU IP scales from 8 GOPS to 80 TOPS

Cadence Neo NPU (Neural Processing Unit) IP delivers 8 GOPS to 80 TOPS in single core configuration and can be scaled to multicore configuration for hundreds of TOPS.

The company says the Neo NPUs deliver high AI performance and energy efficiency for optimal PPA (Power, Performance, Area) and cost points for next-generation AI SoCs for intelligent sensors, IoT, audio/vision, hearables/wearables, mobile vision/voice AI, AR/VR and ADAS.

Some highlights of the new Neo NPU IP include:

• Scalability – Single-core solution is scalable from 8 GOPS to 80 TOPS, with further extension to hundreds of TOPS with multicore
• Supports 256 to 32K MACs per cycle to allow SoC architects to meet power, performance, and area (PPA) tradeoffs
• Works with DSPs, general-purpose microcontrollers, and application processors
• Support for Int4, Int8, Int16, and FP16 data types for CNN, RNN and transformer-based networks.
• Up to 20x higher performance than the first-generation Cadence AI IP, with 2x to 5x the inferences per second per area (IPS/mm2) and 5x to 10x the inferences per second per Watt (IPS/W)
• Typical clock frequency of 1.25 GHz with a 7nm process

Cadence provides a NeuroWeave Software Development Kit (SDK) that works with the company’s AI and Tensilica IP products and enables no-code AI development.  The SDK is said to support various Machine Learning (ML) frameworks such as TensorFlow, ONNX, PyTorch, Caffe2, TensorFlow Lite, MXNet, JAX, as well as the Android Neural Network Compiler, TF Lite Delegates for real-time execution, and TensorFlow Lite Micro for microcontroller-class devices.

The Neo NPU IP and the NeuroWeave SDK are expected to become available in December 2023, meaning the first SoCs with a Neo NPU would likely launch sometime in the second half of 2024. Additional information may be found on the product page and the press release.

Thanks to TLS for the tip.

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