Achronix Speedster7t AC7t1500 FPGA is now available for high-bandwidth applications

Achronix Semiconductor has recently announced the general availability of the Speedster7t AC7t1500 FPGA designed for networking, storage, and compute (AI/ML) acceleration applications.

The 7nm Speedster7t FPGA family offers PCIe Gen5 ports and GDRR6 and DDR5/DDR4 memory interfaces, delivers up to 400 Gbps on the Ethernet ports, and includes a 2D network on chip (2D NoC) that can handle 20 Tbps of total bandwidth.

Achronix Speedster7t highlights:

• Two-dimensional network on chip (2D NoC) enabling high bandwidth data flow throughout and between the FPGA fabric and hard I/O and memory controllers and interfaces
• MLP (Machine Learning Processors) blocks with arrays of multipliers, adder trees, accumulators, and support for both fixed and floating-point operations, including direct support for Tensorflow’s bfloat16 format and block floating-point (BFP) format.
• Multiple PCIe Gen5 ports
• High-speed SerDes transceivers, supporting 112 Gbps PAM4 and 56 Gbps PAM4/NRZ modulation, as well as lower data rates
• Hard Ethernet MACs that support up to 400 Gbps
• GDDR6 and DDR5 SDRAM controllers and interfaces (Note: the Speedster7t AC7t1500 supports DDR4 rather than DDR5)
• Security
  • Fabric-based bi-directional cryptographic engine (Speedster7t AC7t1550)
  • Hard bi-directional cryptographic engine (Speedster7t AC7t800 and others)
• Logic architecture with 6-input LUTs (6LUT), 8-bit ALUs, flip-flops, and a reformulated multiplier LUT (MLUT) mode based on a modified Booth’s algorithm, which doubles the performance of LUT-based multiplication
• Fabric routing enhanced with dedicated bus routing and active bus muxing
• 72 kb BRAM and 2 kb LRAM memory blocks
• GPIO supporting multiple I/O standards
• PLLs and DLLs to support multiple, on-chip clock trees
• Multiple types of programming interfaces
• Partial reconfiguration of the FPGA fabric
• Remote update of the FPGA fabric
• Security features for encrypting and authenticating bitstreams
• Debug support through Achronix Snapshot

There are five parts in the Speedster7t product matrix with the 7t1500 with 692K LUTs now in mass production and the entry-level 7t800 with 326 LUTs having just been added to Achronix Tool Suite. The higher-end 7t3000 and 7t6000 parts must be planned for the future as they are not listed in the datasheet yet.

I could not find any typical development board for the Speedster7t FPGAs, but the company provides the VectorPath S7t-VG6 accelerator card based on the 7t1500 FPGA. It is designed for the development of high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking, and data center applications.

Main interfaces and specifications:

• FPGA – Speedster7t AC7t1500 FPGA
• System Memory
  • GDDR6 – 16 GB, 8 banks with two independent 16-bit channels per bank
  • One bank of DDR4 – 2666 MHz with ECC, up to 4 GB (×72)
• Storage – Flash memory for booting FPGA
• PCI SIG certified to support PCIe Gen4 x16 host interface
• 1x QSFP-DD cage – 1x 400GbE, 2x 200GbE, 4x 100GbE, or 8x 10/25/40/50 GbE
• 1x QSFP56 cage – 1x 200GbE, 2x 100GbE, or 4x 10/25/40/50 GbE
• 8x GPIO
• MCIO – connected to FPGA via four transceivers supporting up to PCIe Gen5 data rates

The Achronix Tool Suite is used for all Achronix FPGAs and eFPGA IP solutions and comes with the company’s ACE design tools and Synopsys Synplify-Pro for the synthesis of FPGA designs. Achronix simulation libraries are supported by Mentor Graphics ModelSim, Synopsys VCS, and Aldec Riviera-PRO, and the suite also includes the Snapshot Debugger real-time design debugging tool. The design flow should be straightforward to FPGA designers used to working on competing FPGA with support for VHDL and Verilog input, and industry-standard simulation.

Additional information may be found on the product page and press release.

Thanks to TLS for the tip.

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