Allwinner V851S/V851SE low-cost camera SoC embeds 64MB DDR2, a 0.5 TOPS NPU

Allwinner V851S/V851SE is a single-core Arm Cortex-A7 SoC with a RISC-V core, an H.265/H.264 video encoder, and a 0.5 TOPS NPU designed for Smart IP cameras with support for features such as human detection and crossing alarms.

Both processors ship with 64MB DDR2 memory, and feature USB, Ethernet, and SDIO interfaces, but the V851S is designed for systems with a display, while the V851SE targets traditional headless IP cameras.

Both processors are pretty similar, but here are the key differences between Allwinner V851S:

• Networking – 10/100 Mbps Ethernet port with RMII interface
• GPIO – 6x ports (PA, PC, PD, PE, PF, PH)
• Display
  • LCD Parallel RGB, Serial RGB, i8080, BT656
  • 2-lane MIPI DSI
• SPI – 4x SPI

and Allwinner V851SE:

• Networking – SIP 100 Mbps EPHY
• GPIO – 5x ports (PA, PC, PE, PF, PH)
• Display – Not supported
• SPI – 3x SPI

That means the Allwinner V851S requires an Ethernet PHY on the board, but it is built into the Allwinner V851SE for more cost-effective designs.

Allwinner V851S and V851SE specifications:

• CPU
  • Arm Cortex-A7 CPU core @ 900 MHz
  • RISC-V core @ 600 MHz
• Memory – 64MB DDR2 on-chip
• Storage I/F – 3x SMHC for eMMC/SDHC, SPI NAND/NOR flash interface
• AI accelerator – 0.5 TOPS NPU supporting TensorFlow, Caffe, Tflite, Pytorch, ONNX, etc..
• Video Encoding/Decoding
  • H.264/H.265 encoder up to 3840×2160 @ 20fps
  • H.264/H.265 multi-stream real-time encoding capability: 5M @ 25fps + 720p @ 25fps
  • JPEG encoder 1080p60
• Video Output (V851S only)
  • 2-lane MIPI DSI up to 1280×720 @ 60fps
  • TCONLCD interface
    • i8080 interface, up to 800×480 @ 60fps
    • Serial RGB interface, up to 800×480 @ 60fps
    • RGB interface with DE/SYNC mode, up to 1920×1080 @ 60fps
• Video Input
  • ISP with maximum resolution of 2560 x 1440, up to 4Mbps @ 30fps
  • 10-bit Parallel CSI interface up to 4x 720p30
  • 4-lane MIPI CSI input or two 2-lane MIPI CSI inputs up to 4Mbps @ 30 fps
• Audio
  • DAC supporting 16-bit and 20-bit sample resolution, 8 kHz to 192 kHz DAC sample rate
  • ADC supporting 16-bit and 20-bit sample resolution, 8 kHz to 48 kHz ADC sample rate
  • Audio input  – 1x differential microphone input (MICIN1P/N)
  • Audio output – 1x single-ended lineout output: (LINEOUTLP)
  • 1x I2S/PCM external interface for connecting external power amplifier and MIC ADC
  • DMIC – Up to 8x digital PDM microphones with sample rates from 8 kHz to 48 kHz
• Networking
  • V851S – 10/100M Fast Ethernet with RMII interface
  • V851SE – SIP 100M EPHY
• USB – USB 2.0 DRD
• Other peripheral interfaces – 5x TWI/I2C, 4x UART, up to 4x SPI, up to 6x GPIO “groups”, general-purpose analog-to-digital converter(GPADC), 11-channel PWM
• Security System
  • Crypto Engine with symmetrical algorithms for encryption and decryption (AES, DES, 3DES), hash algorithms for tamper proofing (MD5, SHA, HMAC), public key algorithms, 160-bit hardware PRNG, 256-bit hardware TRNG
  • Security ID (SID) – 2048-bit eFuse
  • V851S/V851SE appear to have gotten Level 1 PSA certification
• Package – QFN88, 9 x 9 mm, 0.35mm ball pitch

Allwinner V851S and V851S3 are low-cost versions of the Allwinner V853 or V853S which feature a Cortex-A7 processor @ 1.2 GHz, an Alibaba Xuantie E907 RISC-V core, and an up to 1 TOPS NPU, as well as support for external memory.

You’d usually select the V851S if you need a display, and the V851SE for cameras without a display. There’s no product page on the Allwinner website, just a short announcement in Chinese, but the datasheet is available on the company’s forum and that’s where I got most of the information above. The processor runs Tina Linux, a fork of OpenWrt for Allwinner processors.

I found out about the new processor through the YuzukiHD board made by the same developer (GLGH_) that did the Yuzuki Chameleon board with an Allwinner H616 processor.

It comes with a USB Type-C port, a MicroSD card socket for the OS, two buttons, and connectors for a camera and a display as shown above.

The silkscreen shows the board is open-source hardware, so I’d expect the hardware design files and other resources to be released on YuzukiHD’s Github account in due time.

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