Acromag XMC-7A50-AP323 – An XMC module based on AMD Xilinx Artix-7 FPGA

Acromag XMC-7A50-AP323 is an XMC (Switched Mezzanine Card) module based on a Xilinx Artix-7 FPGA with 48 TTL I/O channels plus a 16-bit ADC for 20 differential or 40 single-ended analog inputs.

Designed for commercial off-the-shelf (COSTS) applications, Acromag XMC modules are RoHS compliant, and suitable for automation applications, scientific development labs, as well as aerospace and military applications.

Acromag XMC-7A50-AP323 module specifications:

• FPGA – AMD Xilinx Artix-7 (XC7A050) FPGA with 52,160 logic cells, 65,200 Flip flops, 2,700 kb block RAM, 120 DSP slices
• Storage – 32Mbit QSPI flash memory
• FPGA Digital I/O
  • 48x I/O channels controlled in groups of eight channels, 5V tolerant
  • TTL, RS485, and LVDS interface options:
    • Build Option A: 24x EIA-485/422 channels
    • Build Option B: 24x TTL and 12x EIA-485/422 channels
    • Build Option C: 24x LVDS channels
• Analog Input
  • 20 differential or 40 single-ended inputs
  • Flexible scan control
  • 16-bit A/D resolution
  • 8μs conversion time
  • FIFO buffer with 16K sample memory
  • Interrupt upon FIFIO threshold condition
  • FIFO full, empty and threshold reached flags
  • Programmable channel conversion control
  • Programmable conversion timer
  • Several scanning modes
  • External trigger
• Field I/O Interface – PCIe bus 1 lane Gen 1 interface.
• I/O Connector – 100-pin field I/O connector
• Misc – External LVTTL clock input
• Dimensions – 143.75 x 74 mm
• XMC Compliance
  • ANSI/VITA 42.0 specification for XMC module mechanicals and connectors.
  • ANSI/VITA 42.3 specification for XMC modules with PCI Express interface.
  • Electrical/Mechanical Interface – Single-width module.
• Weight – About 100 grams
• Temperature Range – Operating: -40 to 70°C, storage: -55 to 100°C

 

The FPGA can be programmed with Xilinx Vivado® design tools, and the company provides software development tools for VxWorks, Linux, and Windows environments, as well as an example FPGA program described as follows:

IP integrator block diagram provided for PCIe bus 1 lane Gen 1 interface, DMA controller, on chip block RAM, flash memory and control of field I/O.

It is part of an Engineering Design Kit (EDK) software that provides users with the basic information required to develop a custom FPGA program and must be ordered with the first purchase of a XMC-7A50-AP323 series module. Besides the VHDL example, the EDK also includes schematics, parts list, part location drawings, and other utility files.

Acromag XMC-7A50-AP323 module starts at $2,750, with the recommended EDK software adding $360. Further information may be found on the product page and announcement.

Thanks to TLS for the tip

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