Efinix Releases Three RISC-V Software-Defined SoC’s Optimized for Trion FPGA’s

Efinix has announced three RISC-V Software-defined SoC’s based on Charles Papon’s VexRiscv core and optimized for the company’s Trion T8 to T120 FPGA’s.

VexRiscv is a 32-bit RISC-V CPU using  RISCV32I ISA with M and C extensions, has five pipeline stages (fetch, decode, execute, memory, and writeback), and a configurable feature set. Each SoC includes a RISC-V core, memory, as well as various I/O and interfaces.

Key features for each of three RISC-V SoC’s:

• Ruby SoC
  • FPGA footprint – ~12K LEs/78 RAM blocks
  • Performance – 50 MHz (1.16 DMIPS/MHz)
  • Memory – 4 KB on-chip RAM, up to 3.5 GB DDR DRAM
  • Peripherals – 16x GPIO, Timer, PLIC, 3x SPI masters, 3x I2C masters/slaves, 2x UARTs
  • 1x AXI4, 2x APB3 user peripherals
  • Target applications – real-time system controls and image signal processing.
• Jade SoC
  • FPGA footprint – ~7K LEs/93 RAM blocks
  • Performance – 50 MHz (1.2 DMIPS/MHz)
  • Memory – 32 KB on-chip RAM
  • Peripherals – 16x GPIO, Timer, PLIC, 2x SPI masters, 2x I2C masters/slaves, 1x UART
  • 1x APB3 user peripheral
  • Target applications – Command and control, industrial automation or data logging
• Opal SoC
  • FPGA footprint – ~5K LEs/16 RAM blocks
  • Performance – 50 MHz/20 MHz (0.98 DMIPS/MHz)
  • Memory – 4 KB on-chip RAM
  • Peripherals – 8x GPIO, Timer, PLIC, 1x SPI master, 1x I2C master/slave, 1x UART
  • 1x APB3 user peripheral
  • Target Applications – System monitoring or remote configuration and control.

For each SoC, the company provides the SoC RTL files, a board support package (BSP), sample code, and an SDK based on the Eclipse IDE, GCC toolchain, and OpenOCD debugging.

Efinity software would also allow you to build your own RTL designs based  Ruby, Jade, or Opal RISC-V SoC for one of Efinix Trion development boards.

You’ll find further information and links to download the RISC-V SoC files (free email registration required) on the product page.

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