soc

Posted on by Jean-Luc Aufranc (CNXSoft) - 8 Comments on SiFive U54-MC Coreplex is the First Linux Ready RISC-V based 64-bit Quad-Core Application Processor

SiFive U54-MC Coreplex is the First Linux Ready RISC-V based 64-bit Quad-Core Application Processor

We first covered SiFive when they unveiled their open source Freedom RISC-V SoCs. Since then, they moved away from open source for their customizable IP, since their customers did not require fully open source designs, but kept releasing more RISC-V cores such as 32-bit E31 Coreplex & 64-bit E51 Coreplex, as well as offering their one-time fee pricing without recurring royalties, contrary to what some competitors – such as Arm – are doing. The company has now just announced U54-MC Coreplex quad core real-time capable application processor with support for full featured operating systems such as Linux. U54-MC Coreplex main specifications / features: Fully compliant with the RISC-V ISA specification 4x RV64GC U54 Application Cores 32KB L1 I-cache with ECC, 32KB L1 D-cache with ECC 8x Region Physical Memory Protection 48x Local Interrupts per core Sv39 Virtual Memory support with 38 Physical Address bits 1x RV64IMAC E51 Monitor Core 4KB […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 8 Comments on Qualcomm Provides Details about 64-bit ARM Falkor CPU Cores used in Centriq 2400 Server-on-Chip

Qualcomm Provides Details about 64-bit ARM Falkor CPU Cores used in Centriq 2400 Server-on-Chip

Qualcomm officially announced they started sampling Centriq 2400 SoC with 48 ARMv8 cores for datacenters & cloud workloads using a 10nm process, but at the time the company did not provide that many details about the solution or the customization made to the CPU cores. Qualcomm has now announced that Falkor is the custom CPU design in Centriq 2400 SoC with the key features listed by the company including: Fully custom core design – Designed specifically for the cloud datacenter server market, with a 64-bit only micro-architecture based on ARMv8 (Aarch64). Scalable building block – The Falkor core duplex includes two custom Falkor CPUs, a shared L2 cache and a shared bus interface to the Qualcomm System Bus (QSB) ring interconnect. Designed for performance, optimized for power 4-issue, 8-dispatch heterogeneous pipeline designed to optimize performance per unit of power, with variable length pipelines that are tuned per function to maximize […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on Qualcomm Snapdragon 845 Octa-core Processor To Feature ARM Cortex A75 Cores (Reports)

Qualcomm Snapdragon 845 Octa-core Processor To Feature ARM Cortex A75 Cores (Reports)

According to reports from China, Qualcomm’s next application processor (or rather mobile platform) will be Snapdragon 845, and if accurate, the comparison table below between the Snapdragon processor and Hisilicon Kirin 970 SoC shows the former will be powered by some customized (魔改) version of yet-to-be announced ARM Cortex 75 cores. Snapdragon 845 octa-core processor will be manufactured using Samsung 10nm LPE processor, come with four custom Cortex A75 cores, four Cortex A53 cores, an Adreno 630 GPU, and an LTE X20 modem supporting LTE Cat 18 for up to 1.2 Gbps download speed. Other features like 802.11ad (High bandwidth, short range WiFi), UFS 2.1, and LPDDR4X were already found on earlier model. I’ve been unable to find further details about ARM Cortex A75 right now, and we have to wait until ARM Techcon 2017 before getting more details. Mobile phones powered by Snapdragon 845 are supposed to start shipping […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on SiFive Launches 32-bit E31 Coreplex & 64-bit E51 Coreplex RISC-V Processors, Reveals Pricing

SiFive Launches 32-bit E31 Coreplex & 64-bit E51 Coreplex RISC-V Processors, Reveals Pricing

SiFive unveiled their Freedom U500 and E500 open source RISC-V SoCs last year, and a little layer launched HiFive1 Arduino compatible development board based on SiFive Freedom E310 processor. The company has now launched their non-open source Coreplex IP also based on RISC-V ISA with the 32-bit E31 Coreplex and 64-bit E51 Coreplex, and explained details about pricing. Some of the key features of the processors are listed below: E31 Coreplex 32-bit RV32IMAC core @ 900 to 1.5 GHz (with 28nm process) Advanced Memory Subsystem – 16KB, 2-way Instruction Cache, Instruction Tightly Integrated Memory (ITIM) option, up to 64KB Data Tightly Integrated Memory (DTIM) support Up to 16 local interrupts with vectored addresses Performance – 1.61 DMIPS/MHz  ; 2.73 Coremark/MHz Power Consumption 28nm HPC process – Core only: 150 DMIPS/mW ; Coreplex: 41 DMIPS/mW 55nm LP process – Core only: 95 DMIPS/mW; Coreplex: 16 DMIPS/mW Applications: Edge Computing, Smart IoT […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

Imagination has just unveiled the successor of MIPS I6400 64-Bit Warrior Core with MIPS Warrior I-class I6500 heterogeneous CPU supporting up to 64 cluster, with up to 6 cores each (384 cores max), themselves up to 4 thread (1536 max), combining with IOCU (IO coherence units), and external IP such as PowerVR GPU or other hardware accelerators. The main features of MIPS I6400 processor are listed as follows:   Heterogeneous Inside – In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels. Heterogeneous Outside – The latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 8 Comments on Amlogic S905L Processor Drops VP9 Codec, TS Inputs for Tuners, and the Camera Interface

Amlogic S905L Processor Drops VP9 Codec, TS Inputs for Tuners, and the Camera Interface

[Update: I’ve received updated documentation for Amlogic S905X too, and the main differences are only the lack of VP9 codec, and HDMI 2.0b interface] Amlogic has apparently decided to launch yet another quad core Cortex A53 processor with Amlogic S905L, which appears to be based on  Amlogic S905X with built-in stereo audio codec and 10/100M Ethernet PHY & MAC, HDR support, but without VP9 codec, camera interface, nor TS inputs, so it looks like a cost-down version purely designed for OTT/IP TV boxes. The document I have is dated June 2016, before the 1.5 GHz “limit” was discovered on Amlogic processors, and the maximum frequency is rated @ 2.0 GHz in the document. Amlogic S905L specifications (based on S905L Quick Referent Manual): CPU – Quad core ARM Cortex-A53 CPU up to 2GHz (DVFS) with Neon and Crypto extensions, unified L2 cache 3D GPU – Penta-core ARM Mali-450 GPU up to […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

Open source used to be a software thing, with the hardware design being kept secret for fear of being copied, but companies such as Texas Instruments realized that from a silicon vendor perspective it would make perfect sense to release open source hardware designs with full schematics, Gerber files and SoM, to allow smaller companies and hobbyists, as well as the education market, normally not having the options to go through standard sales channels and the FAE (Field Application Engineer) support, to experiment with the platform and potentially come up with commercial products. That’s exactly what they did with the Beagleboard community, but there’s still an element that’s closed source, albeit documented: the processor itself. But this could change soon, as SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller. Freedom […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on FOSDEM 2015 Schedule – January 31 – February 1 2015

FOSDEM 2015 Schedule – January 31 – February 1 2015

FOSDEM (Free and Open Source Software Developers’ European Meeting) takes place every year during the first week-end of February. This year the developer-oriented event expects to bring over 5000 geeks to share ideas and collaborate on open source projects. Contrary to most other events, it’s free to attend, and you don’t even need to register, just show up. FOSDEM 2015 will take place on January 31- February 1 in Brussels. There will be 551 sessions divided into 5 keynotes, 40 lightning talks, 6 certification exams, and with the bulk being developer rooms and main tracks,  divided into 7 main tracks this year: Languages, Performance, Time, Typesetting, Hardware, Security and Miscellaneous. I’m not going to attend, but it’s still interested to see what will be talked about, and I’ve concocted my own little virtual program out of the main tracks and developers’ rooms. There’s a few minutes overlap between some talks […]

UP 7000 x86 SBC