server News - Page 9 of 26 - CNX Software

November 27, 2018November 27, 2018 by Jean-Luc Aufranc (CNXSoft) - 31 Comments

Amazon Launches 64-bit Arm Server “A1” Instances

Amazon has developed AWS Graviton processors optimized for cloud applications and delivering power, performance, and cost optimizations over their Intel counterpart. The processors feature 64-bit Arm Neoverse cores and custom silicon designed by AWS themselves, and can be found today in Amazon EC2 A1 instances. The screenshot above shows Amazon Linux 2, Red Hat Enterprise Linux 7.6, Ubuntu 18.04 Server, and Ubuntu 16.04 Server machine images having options for either 64-bit x86 or 64-bit Arm servers. Amazon Arm server instance are particularly suitable for applications such as web servers, containerized microservices, caching fleets, distributed data stores, as well as development environments. Amazon further explains: A1 instances are built on the AWS Nitro System, a combination of dedicated hardware and lightweight hypervisor, which maximizes resource efficiency for customers while still supporting familiar AWS and Amazon EC2 instance capabilities such as EBS, Networking, and AMIs. Amazon Linux 2, Red Hat Enterpise Linux […]

November 21, 2018 by Jean-Luc Aufranc (CNXSoft) - 19 Comments

HiSilicon Hi1620 Server SoC to Features up to 64 Arm “Ares” Cores

A few years ago we covered Hisilicon D02 server board powered by the company’s Hip05 SoC with 16 or 32 Arm Cortex A57 cores. I had not seen any updates since then myself, but HiSilicon has released new “TaiShan” Arm based server SoCs every year, and recently unveiled Hi1620, the world’s first 7nm datacenter Arm processor, featuring 24 to 64 Arm “Ares” cores clocked at up to 3.0 GHz. Ares cores are supposed to greatly improve single thread performance in order to compete with x86 server chips. HiSilicon Hi1620 processors specifications: CPU – 24 to 64 Ares ARMv8.2 cores clocked at 2.4 – 3.0 GHz Cache – L1: 64KB I-cache, 64KB D-cache; L2: 512KB private per core, L3: 24-64 shared among cores (1MB/core) Memory – 8x DDR4 channels up to 3200 MHz Interconnect – Coherent SMP interface for 2S & 4S, 3 ports up to 240 Gbit/s per port I/Os […]

October 17, 2018 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Arm ServerReady is a Compliance Program for Arm-based Servers

The Server Base System Architecture (SBSA) specification was unveiled in 2014 in order to standardize all Arm based servers and let them all run the same operating system images. However so far, manufacturers would just test specification requirements by themselves without having their claims fully tested and certificated. That’s why Arm has just unveiled the Arm ServerReady certification program for Arm based servers which relies on the Architecture Compliance Suite (ACS) for SBSA and SBBR (Server Base Boot Requirements) verification. Basically the servers must be able to boot standard operating systems and run the ACS. The servers that pass the ACS are then granted the Arm ServerReady certificate. The current Arm ServerReady version 1.0 certification utilizes ACS version 1.6 for testing SBSA version 3.1 and SBBR version 1.0 compliance. Ampere, HXT, Marvell, Qualcomm, as well as ODMs such as Femrice, Gigabyte and UIT have already received Arm ServerReady version 1.0 […]

August 28, 2018August 28, 2018 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

VMWare Showcases ESXi Bare Metal Hypervisor Support for ARM64 Edge Servers

As I checked my Twitter timeline in Thunderbird this morning, I started to see a lot of tweets about #VMworld2018 and “ESXi on 64-bit Arm”. What is that? VMWare has just announced and showcased several technology innovations at VMworld 2018, including Virtualization on 64-bit ARM for Edge, and the company demonstrated ESXi on 64-bit ARM running on a windmill farm at the Edge. It may be useful to readers (and this writer) to look up what ESXi is and does exactly. As explained on VMWare website: VMware ESXi is a purpose-built bare-metal hypervisor that installs directly onto a physical server. With direct access to and control of underlying resources, ESXi is more efficient than hosted architectures and can effectively partition hardware to increase consolidation ratios and cut costs for our customers. So basically it’s an hypervisor that stays a close as possible to the hardware to keep performance optimal, and […]

August 27, 2018 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

MicroWebSrv Lightweight HTTP Web Server Supports HTML/Python Language Templating

There are many languages that can be used to create a web page: HTML, HTML5, JavaScript, PHP, etc… But Python? Apparently yes, as MicroWebSrv lightweight web server – mostly designed for ESP32 platforms running MicroPython such as Pycom boards – supports inserting Python code inside “HTML” files with the extension .pyhtml. The code can be found in Github, and is only comprised of three files. microWebSrv.py – The Web server microWebSocket.py – The optional support of WebSockets microWebTemplate.py – The optional templating language for .pyhtml rendered pages Beside HTML/Python files, the web server can handle GET, POST, … requests, an embedded full REST API, routing handlers, WebSockets, etc… That’s what a mixed HTML + Python .pyhtml file may look like:

<html>
  <head>
    <title>TEST PYHTML</title>
  </head>
  <body>
    <h1>BEGIN</h1>
    {{ py }}
      def _testFunction(x) :
        return "IN TEST FUNCTION %s" % x
    {{ end }}
    <div style="background-color: black; color: white;">
      {{ for toto in range(3) }}
        This is an HTML test...<br />
        TOTO = {{ toto + 1 }} !<br />
        {{ for toto2 in range(3) }}
          TOTO2 = {{ _testFunction(toto2) }}
        {{ end }}
        Ok good.<br />
      {{ end }}
    </div>
    {{ _testFunction(100) }}<br />
    <br />
    {{ if 2+5 < 3 }}
      IN IF (1)
    {{ elif 10+15 != 25 }}
      IN ELIF (2)
    {{ elif 10+15 == 25 }}
      IN ELIF (3)
    {{ else }}
      IN ELSE (4)
    {{ end }}
  </body>
</html>

<html>

<head>

<title>TEST PYHTML</title>

</head>

<body>

<h1>BEGIN</h1>

def _testFunction(x) :

return "IN TEST FUNCTION %s" % x

This is an HTML test...<br />

TOTO = {{ toto + 1 }} !<br />

TOTO2 = {{ _testFunction(toto2) }}

Ok good.<br />

</div>

{{ _testFunction(100) }}<br />

<br />

IN IF (1)

IN ELIF (2)

IN ELIF (3)

IN ELSE (4)

</body>

</html>

You can use double curly braces {{ and }} to insert MicroPython code, if statements, for loops, or includes. I’m not sure if this makes really sense for all […]

April 14, 2018April 14, 2018 by Jean-Luc Aufranc (CNXSoft) - 7 Comments

Optimizing JPEG Transformations on Qualcomm Centriq Arm Servers with NEON Instructions

Arm servers are already deployed in some datacenters, but they are pretty new compared to their Intel counterparts, so at this stage software may not always be optimized as well on Arm as on Intel. Vlad Krasnow working for Cloudflare found one of those unoptimized cases when testing out Jpegtran – a utility performing lossless transformation of JPEG files – on one of their Xeon Silver 4116 Server:

vlad@xeon:~$ time  ./jpegtran -outfile /dev/null -progressive -optimise -copy none test.jpg

real    0m2.305s
user    0m2.059s
sys     0m0.252s

vlad@xeon:~$ time ./jpegtran -outfile /dev/null -progressive -optimise -copy none test.jpg

real 0m2.305s

user 0m2.059s

sys 0m0.252s

and comparing it to one based on Qualcomm Centriq 2400 Arm SoC:

vlad@arm:~$ time ./jpegtran -outfile /dev/null -progressive -optimise -copy none test.jpg

real    0m8.654s
user    0m8.433s
sys     0m0.225s

vlad@arm:~$ time ./jpegtran -outfile /dev/null -progressive -optimise -copy none test.jpg

real 0m8.654s

user 0m8.433s

sys 0m0.225s

Nearly four times slower on a single core. Not so good, as the company aims for at least 50% of the performance since the Arm processor has double the number of cores. Vlad did some optimization on The Intel processor using SSE instructions before, so he decided to look into optimization the Arm code with NEON instructions instead. First step was to check which functions may slowdown the […]

April 10, 2018April 10, 2018 by Jean-Luc Aufranc (CNXSoft) - No Comments

Advantech and SocioNext Collaborate for 8K 60Hz Real-Time HEVC Video Encoding, Streaming, and Decoding Solutions

The first live event to be broadcasted in 8K resolution should be the Tokyo Olympic Games in 2020, but but broadcasters will use large and expensive infrastructure equipment to achieve this feat. However, the cost of this solution will be prohibitive for most other situations, so Advantech and SocioNext have collaborated to provide more affordable solutions for live 8Kp60 HEVC video encoding and decoding. One of those solution is Advantech VEGA-3304 that is said to be the first 8Kp60 HEVC acquisition encoder, and comes with 16 x SDI-3G inputs Key features: 1-ch 8Kp60, 4-ch 4Kp60 or 16-ch 1080Kp60 HEVC real-time encoding in Main 8, Main 10 4:2:2 modes Video acquisition over built-in 16-ch 3G-SDI inputs HDR support Double width, ¾ length PCI Express x16, compatible with server GPU slots The PCIe card supports Linux and Windows, and simple-to-use API and example code for FFmpeg and GStreamer multimedia are provided. It can […]