GreenWaves GAP8 is a low power RISC-V “MCU class” processor with eight compute cores optimized for artificial intelligence applications, and its main selling point is the ability to do tasks like computer vision or audio processing at very low power, even good enough to run on batteries. When we first covered GAP8 RISC-V processor at the beginning of the year, the company also mentioned a development kit comprised of GAPDUINO Arduino compatible board, a sensor board, and a QVGA camera module to experiment with the solution. The board and development kit are now easier to purchase as the devkit is sold on SeeedStudio for $229. GAPuino board specifications: SoC – GAP8 IoT Application Processor with 8x RISC-V compute cores, 1x RISC-V fabric controller core delivering up to 200 MOPS at 1mW and >8 GOPS at a few tens of mW Memory / Storage – HyperBus combo DRAM/Flash with 512 Mbit […]
Arm Compares Arm & RISC-V Benefits in RISCV Basics Website
Arm is a dominant force in mobile and embedded processors, but recently we’ve heard more and more about RISC-V open source and royalty-free alternatives, and for example SiFive has launched both application processors / IP with solutions like Linux capable Freedom U540 SoC found in HiFive Unleashed board, as well as RISC-V MCU Cores competing with Arm Cortex-M4 and Cortex-M0+ cores. There’s certainly a lot of activity around RISC-V, but I have not seen many commercial solutions yet, and the platform needs to mature. However, Arm apparently takes the competition seriously with the company setting up a website – riscv-basics.com – comparing Arm and RISC-V, notably through the infographics below. Arm recognizes RISC-V has no recurring license fees, but claims those fees are only a small fraction of the total investment required for a commercial processor. The company also questions RISC-V maturity, and at this stage is may be true, […]
SiFive Announces E20 and E21 RISC-V Cores for IoT and Wearables
SiFive has just announced the availability of their new E2 Core IP Series low-area, low-power microcontroller cores designed for use in embedded devices. Two standards cores are currently part of the new family: E21 providing mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications SiFive E20 MCU Core SiFive E20 Standard Core IP Key Features: RISC-V ISA – RV32IMC Machine Mode only 2-stage pipeline System Port for external memory accesses Core Local Interrupt Controller (CLIC) with 32 interrupts Advanced debug with 4 hardware breakpoints/watchpoints Performance – 1.1 DMIPS/MHz; 2.4 CoreMark/MHz Power / Clock / Area 28nm HPC – 0.58 mW; 725 MHz and up; 0.023 mm2 55nm LP – 1.3 mW; 250 MHz and up; 0.064 mm2 The company compares E20 core to Arm Cortex-M0+ core in the […]
HiFive Unleashed RISC-V Linux Development Board Gets a $2000 FPGA Expansion Board
If you’re a RISC-V architecture’s enthusiast or represent a company working on products with the new ISA, you may have spent $999 or more on Hifive Unleashed RISC-V Linux development board a few months ago. You now have the opportunity to spend an extra $1,999 for HiFive Unleashed Expansion Board powered by a MicroSemi PolarFire FPGA programmed with a PCIe root port bridge, and allowing you to test all sorts of peripherals such as HDD’s & SSD’s, HDMI output, and audio cards, network adapters, graphics cards, and so on. Expansion board specifications: FPGA – Microsemi Low Power PolarFire FPGA with 300K Logic Element 4 Gbit DDR4 x16 SPI Flash for remote FPGA updates, QSPI Flash connected to GPIO 24 lane PCIe Switch x1 PCI Express card connector x16 PCI Express card connector with 4 lanes of PCIe gen2 connected SSD M.2 connector SATA connector HDMI connector eMMC Nand Flash uSD […]
QEMU 2.12 Released with Raspberry Pi 3, RISC-V Support
QEMU is open source machine emulator and virtualizer, which I used in the past at a time when Arm boards were more expensive or hard to get than today, and more recently I tested RISC-V Linux using QEMU (fork). QEMU 2.12 has now been released with some interesting new features including RISC-V support, and initial support for Raspberry Pi 3 machine model. The Changelog is rather long, but some other notable changes include: Cortex-M33 Armv8-M emulation, used by the new mps2-an505 board. Support for various AArch64 v8.1/v8.2/v8.3 extensions. Initial support for Raspberry Pi 3 machine model i.MX7 SoC and i.MX7 Sabre board emulation. Spectre/Meltdown mitigation support for x86/pseries/s390 guest Intel IOMMU support for 48-bit addresses Many SD card emulation cleanups and bugfixes. Etc.. You can get the source code and build instructions in the download page. If you are interested in running Debian on RPI 3 model, or/and want to […]
SiFive Partners with Western Digital to Produce 1 Billion RISC-V Cores
Architecture like Arm and x86 are well established, and initiatives like RISC-V opens source ISA have potential, but market acceptance and commercial success are not guaranteed. But RISC-V just got a big boost, as SiFive announced it raised $50.6 million in a Series C round from existing and new investors, as well as strategic partners such as Huami, SK Telecom and Western Digital. Even more importantly, Sifive and Western Digital signed a multi-year license for the Freedom Platform, with Western Digital pledging to produce 1 billion RISC-V cores. The announcement does not explicitly mention which Freedom platform, but Western Digital statement makes it quite clear they’ll use one of the more powerful (and Linux capable) core: RISC-V delivers a platform for innovation unshackled from the proprietary interface of the past. This freedom allows us to bring compute closer to data to optimize special purpose compute capabilities targeted at Big Data and […]
How to Run Linux on RISC-V with QEMU Emulator
RISC-V open-source architecture is starting to become more and more interesting thanks to the growing RISC-V hardware & software ecosystem, and with the recent release of HiFive Unleashed, we even have a board capable of running Linux. The only problem: it costs $999. But luckily, it’s possible to experiment with Linux on RISC-V without extra hardware, just using your current PC. Imperas offers a commercial solution working on both Windows and Linux that relies on busybear-linux RISC-V Linux root filesystem comprised of busybox and dropbear SSH server. The rootfs also works with QEMU, so I tried it in Ubuntu 16.04. The instructions on Github are quite easy to follow. My computer is powered by an AMD FX8350 processor coupled with 16GB RAM, and the whole process took around 2 hours, so better use the fastest computer possible. It also requires around 26 GB of storage on your build machine. First, […]
RISC-V Keynote at Embedded Linux Conference 2018 (Video)
The Embedded Linux Conference and OpenIoT Summit 2018 have just started, and the Linux Foundation has already uploaded a few keynote videos to YouTube, including the one by Yunsup Lee, Co-Founder and CTO, SiFive, entitled “Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware”. Yunsup explains the current problem with chip development, and go through the open source RISC-V solutions offered by Sifive. Currently design a chip has a high upfront (NRE = non-recurring engineering) costs, is time-consuming (1.5 to 2 years at least) and silicon vendors normally target high volume production, but now many applications like IoT or machine learning require custom chips that may not be (yet) manufactured in such high volume. The solution is to adapt some idea from open source software to open source hardware in order to lower the costs, enable fast prototyping, and involve the community of designers and software developers. He took […]