risc-v News - Page 41 of 51 - CNX Software

February 18, 2020April 30, 2021 by Jean-Luc Aufranc (CNXSoft) - No Comments

Antmicro GEM ASIC Leverages zGlue Technology to Quickly Bring Custom Arm/RISC-V SoC’s to Market

Introduced in 2018, ZiP (zGlue Integration Platform) chip-stacking technology aims to produce chips similar to Systems-in-Package (SiP) but at much lower costs and lead times. We first found it in a Bluetooth tracker featuring ZGLZ1BA custom chip manufactured with zGlue technology and integrating an Arm Cortex-M0 MCU, flash memory and sensors into a single package. But now the technology is back in the news with Antmicro announcing GEM chiplet-based ASIC last December. At the time of the announced the company’s GEM1 chip featured two Lattice iCE40 FPGAs with a MIPI CSI-2 switch, and they had started working on GEM2 chip combining a hard RISC-V processor and Lattice iCE40 FPGA. Those are so-called demonstrators chip as Antmicro customers will be able to easily and quickly design their own 6×9 mm chip(s) with RISC-V and/or ARM CPUs, FPGAs, sensors, radios and other functional elements to meet the requirements of their specific applications. […]

February 17, 2020 by Jean-Luc Aufranc (CNXSoft) - 25 Comments

How to Build & Run Linux on Kendryte K210 RISC-V NOMMU Processor

A few months ago, we wrote that Western Digital was working on Linux & BusyBox RISC-V NOMMU, and managed to boot a minimal Linux OS on Kendryte K210 powered Sipeed Maix Go board. RISC-V NOMMU support was scheduled for Linux 5.5, and now that the new kernel has been released, Damien Le Moal has pushed the code allowing to build Linux and a busybox based roofs for RISC-V 64-bit NOMMU platforms using buildroot. I could start the build following the instructions on Github, but it failed as a Linux 5.6 RC1 tarball was missing. But I noticed “Vowstart” picked up on Damien’s work, and wrote detailed instructions. So let’s try the build out using a machine running Ubuntu 18.04. We’ll have to make sure dependencies are installed first:

sudo apt install build-essential device-tree-compiler bison \
    flex file git curl wget cpio python unzip rsync bc texinfo

1 2	sudo apt install build-essential device-tree-compiler bison \ flex file git curl wget cpio python unzip rsync bc texinfo

Then we can retrieve the source code and do some preparations (e.g. extract Linux 5.6 RC1 tarball):

git clone https://github.com/vowstar/k210-linux-nommu.git
cd k210-linux-nommu
export PROJ_ROOT=$(pwd)
sh ./prepare_buildroot.sh

git clone https://github.com/vowstar/k210-linux-nommu.git

cd k210-linux-nommu

export PROJ_ROOT=$(pwd)

sh ./prepare_buildroot.sh

The next step […]

January 27, 2020January 27, 2020 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Linux 5.5 Release – Main Changes, Arm, MIPS and RISC-V Architectures

Linux 5.5 has just been released by Linus Torvalds: So this last week was pretty quiet, and while we had a late network update with some (mainly iwl wireless) network driver and netfilter module loading fixes, David didn’t think that warranted another -rc. And outside of that, it’s really been very quiet indeed – there’s a panfrost driver update too, but again it didn’t really seem to make sense to delay the final release by another week. Outside of those, it’s all really tiny, even if some of those tiny changes touched some core files. So despite the slight worry that the holidays might have affected the schedule, 5.5 ended up with the regular rc cadence and is out now. That means that the merge window for 5.6 will open tomorrow, and I already have a couple of pull requests pending. The timing for this next merge window isn’t optimal […]

January 26, 2020January 26, 2020 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC’s with Accelerators

FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled “Open ESP – The Heterogeneous Open-Source Platform for Developing RISC-V Systems” with an excerpt of the abstract reading: ESP is an open-source research platform for RISC-V systems-on-chip that integrates many hardware accelerators. ESP provides a vertically integrated design flow from software development and hardware integration to full-system prototyping on FPGA. For application developers, it offers domain-specific automated solutions to synthesize new accelerators for their software and map it onto the heterogeneous SoC architecture. For hardware engineers, it offers automated solutions to integrate their accelerator designs into the complete SoC. If we go to the official website, we can see ESP (Embedded Scalable Platform) actually supports both 32-bit Leon3 (Sparc) and 64-bit Ariane (RISC-V) cores, and various hardware accelerators from the platform or third parties. Highlights: […]

January 8, 2020January 9, 2020 by Ayo Ayibiowu - 6 Comments

ONiO.zero offers a RISC-V Microcontroller that runs without battery

Energy harvesting has been an exciting area people have tried to venture into mostly because of the possible applications that can arise from it. Newly invented energy-harvesting technologies accompanying low-power computing systems have pushed the boundaries of where embedded systems can be deployed. The demand for an increase in connected applications which require an underlying embedded system, and as we know, all electronic devices require a power source of some sort. This power source, batteries in most cases, comes with an accompanying buck regulator of some sort that will tend to increase the BOM. Aside from the BOM rise from the usage of batteries, there is also the shelf life and environmental aspects. The Norwegian specialist ONiO has introduced the ONiO.zero to address those issues. Having no battery means fewer components and a smaller design, which can easily be integrated into a wide range of solutions – be it fabrics, […]

January 2, 2020January 2, 2020 by Jean-Luc Aufranc (CNXSoft) - 10 Comments

Polos GD32V Alef is a Tiny RISC-V MCU Board Selling for $3

We first found out about GigaDevice GD32V 32-bit RISC-V MCU last summer, as an update/alternative to the earlier STM32 compatible GD32 Arm Cortex-M3 microcontroller from the company with higher performance and lower power consumption, while keeping the price identical. The first low-cost GD32V development board we covered was Longan Nano going for $5 with an OLED display and an acrylic case. If you don’t need either or want to access all pins from the 48-pin MCU, you can now order an even cheaper GD32V RISC-V MCU board with Polos GD32V Alef going for $2.99 on Analoglamb website. Polos GD32V Alef board specifications: MCU – Gigadevice GD32VF103CBT6 32-bit RISC-V (rv32imac) microcontroller @ 108 MHz with 128KB Flash, 32KB SRAM USB – 1x micro USB OTG port for power and programming Expansion – 52 through holes (2.54mm pitch) exposing all pins from the MCU including 3x USART, 2x I2C, 3x SPI, 2x […]

December 31, 2019December 31, 2019 by Jean-Luc Aufranc (CNXSoft) - 10 Comments

Year 2019 in Review – Top 10 Posts and Stats

2019 is closing to an end, or you may already be into 2020 while reading this post. In any case, that means it’s time to look back at 2019 and look forward to the events and new products to take place next year. While 2018 was a boring year for new processors, 2019 brought us some interesting new chips such as Amlogic S922X / A311D, or the first Arm Cortex-A55 only processors such as Amlogic S905X3. Rockchip RK3399Pro was promising when it was announced last year, but it never really took off. It was a pretty quiet year for Allwinner as well. RISC-V architecture has been ramping up with the first general-purpose RISC-V MCU: GD32V, WCH CH572 Bluetooth LE MCU, the launch of more SiFive RISC-V cores, and Kendryte K210 RISC-V AI processor announced last year has found its way into more and more boards. There have also been the […]

December 24, 2019 by Jean-Luc Aufranc (CNXSoft) - No Comments

Some Interesting Talks from FOSDEM 2020 Schedule

We wrote about IoT devroom call for proposals for FOSDEM 2020 a little while ago, and as the free open-source developer meetup is getting closer, FOSDEM 2020 organizers released the schedule. So I’ll look at some of the talks in the relevant devrooms such as the Internet of Things, hardware enablement, Embedded, Mobile and Automotive, as well as RISC-V and others to compose my own little virtual schedule for the 2-day event. Saturday, February 1 10:30 – 10:50 – How lowRISC made its Ibex RISC-V CPU core faster – Using open source tools to improve an open-source core – by Greg Chadwick Ibex implements RISC-V 32-bit I/E MC M-Mode, U-Mode, and PMP. It uses an in-order 2 stage pipe and is best suited for area and power-sensitive rather than high-performance applications. However, there is scope for meaningful performance gains without major impact to power or area. This talk describes work […]