Allwinner V853 SoC combines an Arm Cortex-A7 core with a Xuantie E907 RISC-V core, and a 1 TOPS NPU for cost-sensitive AI Vision applications such as smart door locks, smart access control, AI webcams, tachographs, and smart desk lamps. Manufactured with a 22nm process, the SoC comes with an ISP image processor and Allwinner Smart video engine capable of up to 5M @ 30fps H.265/H.264 encoding and 5M @ 25fps H.264 decoding, offers parallel CSI and MIPI CSI camera interfaces, and well as MIPI DSI and RGB display interfaces. Allwinner V853 specifications: CPU Arm Cortex-A7 CPU core @ 1 GHz with 32 KB I-cache, 32 KB D-cache, and 128 KB L2 cache Alibaba Xuantie E907 RISC-V core with 16 KB I-cache and 16 KB D-cache NPU (Neural network Processing Unit) – Up to 1 TOPS for V853 and 0.8 TOPS for V853S, embedded 128KB internal buffer, support for TensorFlow, Caffe, […]
LilyGO T-PicoC3 board merges RP2040 & ESP32-C3, integrates color display
LilyGO T-PicoC3 is a small development board combining Raspberry Pi RP2040 dual-core microcontroller with ESP32-C3 RISC-V MCU to add WiFi and Bluetooth LE connectivity and adds a 1.14-inch color display to the mix, plus several I/Os. We had previously other designs merging ESP32 and RP2040 with UDOO KEY, Arduino Nano RP2040 Connect, or the Pico Wireless Pack among others, but as far as I know, the T-PicoC3 board is the first to use Raspberry Pi RP2040 and ESP32-C3 RISC-V processor. LilyGO T-Pico3 specifications: Microcontrollers Raspberry Pi RP2040 dual-core Cortex-M0+ MCU with 264 KB of embedded SRAM Espressif Systems ESP32-C3 RISC-V processor with WiFi 4 and Bluetooth 5.0 LE connectivity Storage – 4MB SPI flash connected to RP2040 Display – 1.14-inch full-color IPS LCD Display (ST7789V SPI controller) with 240 x 135 resolution USB – USB Type-C port for power and programming (RP2040 / ESP32-C3) Expansion – 15-pin + 12-pin expansion […]
Android RISC-V progress update, emulator support, and roadmap to 2023
We’ve first covered Alibaba T-Head work on Android 10 for RISC-V in January 2021, and later that year they started selling the T-Head RVB-ICE dual-core RISC-V board with GPU for software development. The company has now provided an update for Android 12 RISC-V port, instructions to build Android RISC-V to run it in an emulator, as well as a 2022-2023 roadmap. Alibaba T-head is working on hardware platforms, which appears to be similar to T-Head RVB-ICE board, with the following minimal specifications: CPU – At least Dual-core XuanTie C910 (rv64imafdcv) processor GPU – Compatible with OpenGL ES and OpenCL VPU – HW Video/Picture codec Neural Network Accelerator System Memory – 4GB or more DDR Memory Display – MIPI/HDMI Audio – Multi-Channel Audio output & input Camera – ISP with support for multiple MIPI CSI lanes USB interface(s) They built upon the work done on Android 10 to add support for […]
$10 T-Zigbee board combines ESP32-C3 and TLSR8258 for Zigbee 3.0, WIFi and BLE connectivity
LilyGO T-Zigbee board combines ESP32-C3 WiFi and BLE wireless microcontroller and Telink TLSR8258 multi-protocol wireless SoC compatible with BLE 5 Mesh, Zigbee, RF4CE, Thread, 6LoWPAN, HomeKit, ANT, and 2.4GHz proprietary standards. As I understand it, T-Zigbee is designed to act as a Zigbee to WiFi bridge, and is compatible with Zigbee2MQTT and Home Assistant, allowing easy integration into your home automation setup. Based on the hardware, I’d assume it may be usable as a BLE to MQTT gateway as well, in a fashion similar to GL.inet GL-S10 gateway, for people willing to work on the software/firmware. T-Zigbee specifications: Wireless MCUs Espressif Systems ESP32-C3 RISC-V processor with WiFi 4 and Bluetooth 5.0 LE connectivity Telink Semiconductors TLSR8258 (PDF product brief) Arm Cortex-M0 multiprotocol microcontroller @ 48 MHz with BLE 5 Mesh, Zigbee, RF4CE, Thread, 6LoWPAN, HomeKit, ANT, and 2.4GHz proprietary connectivity Antennas – 2x PCB antennas, 2x u.FL antenna connectors USB […]
ESP32-C2 WiFi & Bluetooth LE 5.0 chip to support Matter WiFi protocol
Espressif ESP32-C2 is a new WiFi 4 and Bluetooth LE 5.0 chip the Shanghai-headquartered company has been working on since last year. The company claims it has better RF performance due to a smaller package reducing stray parasitics, and it will support the Matter protocol whose first version should become ratified later this year. The first ESP32-C2 product wafers have been received by the Shanghai team in spite of the current lockdown and quarantine in Shanghai due to the COVID-19, and teams in other parts of Asia, Europe, and Singapore are working without interruption on software integration into ESP-IDF and ESP-RainMaker. ESP32-C2 preliminary specifications: RISC-V core 272KB of memory Connectivity WiFi 4 + BLE 5.0 Tx power 20 dBm (FCC limit) 18 dBm for 802.11N MC7 packets (72.2 Mbps) Receiver sensitivity – -97 to -100 dBm for 1 Mbps 802.11B packets. Receive current – 58 mA Package – 4 x […]
StarFive releases Perf tool for highest performance RISC-V IP Dubhe (Sponsored)
As a StarFive Technology in-house developed RISC-V 64-bit ultra-high-performance core, Dubhe showcases the best performance RISC-V CPU core IP yet. It utilizes the latest RISC-V instruction set which includes RV64GC, bit operation extension (B), vector extension (V) V1.0, and hypervisor extension H (Hypervisor), making it ideal for high-performance computing. To pair with the Dubhe performance core, StarFive is now releasing “StarFive Perf Performance Profiling Tool”. StarFive has made Perf compatible with the hardware performance monitor (HPM) and micro-architecture events at the hardware level. Perf provides a reliable performance verification platform that not only facilitates customers to further discuss the Dubhe technical specifications but also accelerates the implementation of high-performance applications with RISC-V processors. Perf is an open-source and Linux-based performance analyzing tool capable of providing performance monitoring of the hardware events, tracepoints, firmware events, and dynamic probes. With the Perf profiling tool, we can monitor the performance of the predefined […]
QEMU 7.0 released with support for RISC-V KVM, Intel AMX, and more
QEMU (Quick EMUlator) is an open-source emulator used to run OS or programs on various architectures such as Arm, RISC-V, and many others when you don’t own specific hardware, or for quick testing. The developers have released QEMU 7.0 a few days ago with over 2500 commits from 225 developers. New features include support for RISC-V KVM and vector extensions, Intel AMX (Advanced Matrix Extension), improved flexibility for fleecing backups, various new features for Arm, and many more. QEMU 7.0 highlights listed by the developers: ACPI: support for logging guest events via ACPI ERST interface virtiofs: improved security label support block: improved flexibility for fleecing backups, including support for non-qcow2 images ARM: ‘virt’ board support for virtio-mem-pci, specifying guest CPU topology, and enabling PAuth when using KVM/hvf ARM: ‘xlnx-versal-virt’ board support for PMC SLCR and emulating the OSPI flash memory controller ARM: ‘xlnx-zynqmp’ now models the CRF and APU control […]
SkiffOS minimal Linux for embedded containers now supports Sipeed Nezha RISC-V board
SkiffOS minimal Cross-compiled Linux for embedded containers has just added support for Sipeed Nezha RISC-V single board computer, and work on the smaller Sipeed Lichee RV board has started. Wait… What is SkiffOS? I’ve never heard about it… That’s how the abstract from the white paper describes it: Embedded Linux processors are increasingly used for real-time computing tasks such as robotics and Internet of Things (IoT). These applications require robust and reproducible behavior from the host OS, commonly achieved through immutable firmware stored in read-only memory. SkiffOS addresses these requirements with a minimal cross-compiled GNU/Linux system optimized for hosting containerized distributions and applications, and a configuration layering system for the Buildroot embedded cross-compiler tool which automatically re-targets system configurations to any platform or device. This approach cleanly separates the hardware support from the applications. The host system and containers are independently upgraded and backed-up over-the-air (OTA). In other words, that’s […]