Renesas has recently announced its first homegrown 32-bit RISC-V CPU core based on the open-standard instruction set architecture (ISA). This CPU core is compatible with Renesas’ e2 studio IDE and supports other third-party IDEs for RISC-V MCUs. According to Renesas, the CPU achieved a remarkable 3.27 CoreMark/MHz performance outperforming similar RISC-V architectures in this category. RISC-V, an open ISA, is rapidly gaining popularity in the semiconductor industry. Many MCU providers have formed joint investment alliances to expedite their RISC-V product development. Previously, Renesas released two CPUs developed by Andes Technology Corp: the R9A02G020, an ASSP EASY MCU for Motor Control, and the R9A06G150, an ASSP EASY MCU for Voice HMI, both based on RISC-V. Additionally, they have introduced the RZ/Five, a Linux-capable 64-bit RISC-V microprocessor family, and RH850/U2B, an automotive System on Chip (SoC). However, with the release of their new CPU, Renesas independently enters the RISC-V market, highlighting their […]
Renesas’ first 32-bit RISC-V CPU core delivers up to 3.27 CoreMark/MHz
