We first heard about NXP i.MX 8M processsors in October 2016, and at the end of last year, WandPi 8M development board was unveiled with shipping scheduled for Q2 2018 once the processor will start manufacturing. Other exciting i.MX 8M projects include Purism Librem 5 smartphone, MNT Reform DIY modular computer, and I’m sure there will be others development board & products, and plenty of system-on-modules introduced with the processor in 2018. NXP i.MX 8M processor also got in the news at CES 2018, because it will be one of the hardware platforms certified for Android Things, and NXP also issued a press release to announced the processor’s multimedia capability with be used in voice controlled devices with or without video. The PR refers to Gartner Research saying that “voice commands will dominate 50 percent of all searches in the next two years”, and explains that with thinner and thinner […]
NXP Announces OpenIL Industrial Real-Time Linux Distribution for Industry 4.0
NXP has announced the release of OpenIL industrial Linux distribution with real-time OS extensions and Time-Sensitive Networking (TSN) support for factory-automation for the Industry 4.0 era. The OpenIL distribution includes support for per-stream policing, time-aware shaping of network traffic, and 801.1AS time synchronization, and supports NXP Layerscape SoCs and boards such as LS1028A dual ARMv8 processor, or LS1021A-IOT IoT gateway. Some notable OpenIL features include: Xenomai real-time extensions to Unix, making porting relatively easy from an RTOS like VxWorks or pSOS Extensible Markup Language (XML) and NETCONF-based network configuration utilities for TSN Generalized precision time protocol (gPTP) with the linuxptp daemon Drivers for the Ethernet Interfaces and the NXP SJA1105T TSN switch Support for edge computing services Optional instantiation of the Ubuntu user-space filesystem layout You’ll find the source code on Gihub, and some more information on OpenIL.org website. NXP appears to be the only company involved in the project, […]
Octo SPI / HyperBus Interface is Designed for High Speed Serial Flash, RAM, and MCP
So far, if you needed high speed storage with low pin count in your MCU based board, you could use QSPI (Quad SPI) NOR flash, but earlier this month I wrote about STM32L4+ MCU family, which added two Octo SPI interfaces. I had never heard about Octo SPI previously. Those two interfaces can be used with single, dual, quad, or octal SPI compatible serial flash or RAM, and support a frequency of up to 86 MHz for Octal SPI memories in STM32L4+ MCU. STMicro OctoSPI interface also supports Cypress/Spansion Hyperbus mode to connect to HyperFlash or HyperRAM chip, or even HyperFlash + HyperRAM Multi-Chip packages (MCP), and variable or fixed external memory latency as defined by the Hyperbus protocol specification. The latter reveals Hyperbus supports performance up to 400 MB/s (provided the controller support 200 MHz), and relies on either 11 bus signals using 3.0V I/O (Single-ended clock CK), or […]
Emcraft Releases Linux BSP for NXP i.MX RT1050 Cortex M7 Evaluation Board
NXP iMX RT series is a family of ARM Cortex M7 processors clocked at 600 MHz, making the solution a “crossover embedded processor” bridging the gap between real-time capabilities of micro-controllers and the performance of application processors. This week, NXP provided some benchmark numbers for i.MX RT1050 processor, which delivers a CoreMark score of 3020, DMIPS of 1284, and 20ns interrupt latency at 600 MHz, which means it could be a good candidate for embedded Linux, and Emcraft Systems has just released a uCLinux BSP for the NXP i.MX RT1050 EVK board. The BSP features U-Boot v2017.09-rc1, Linux Kernel 4.5 with relevant device drivers such as key I/O interfaces, Wi-Fi, SD card, LCD, etc…, and GNU development tools such as a GCC 4.7 toolchain, GDB, and so on. The company has made a demo with a GUI application designed with Crank Software’s Storyboard Suite, and running in Linux on the […]
Linaro Connect SF 2017 Welcome Keynote – New Members, Achievements, the Future of Open Source, and More…
Linaro Connect San Francisco 2017 is now taking place until September 29, and it all started yesterday with the Welcome Keynote by George Grey, Linaro CEO discussing the various achievements since the last Linaro Connect in Budapest, and providing an insight to the future work to be done by the organization. The video is available on YouTube (embedded below), and since I watched it, I’ll provide a summary of what was discussed: Welcoming New Members – Kylin (China developed FreeBSD operating systems) joined LEG (Enterprise Group), NXP added LHG (Home Group) membership, and Xilinx joined LITE (IoT and Embedded). Achievements OPTEE open portable trusted environment execution more commonly integrated into products. Details at optee.org. LEG 17.08 ERP release based on Linux 4.12, Debian 8.9 with UEFI, ACPI, DPDK, Bigtop, Hadoop, etc… LITE group has been involved in Zephyr 1.9 release, notably contributing to LwM2M stack More projects to be found […]
NXP RoadLink SAF5400 is a Single Chip Secure DSRC/802.11p V2X Platform
Marvell unveiled 88W8987xA wireless SoC for V2X (Vehicle to Everything) applications supporting 802.11p WiFi, and DSRC (Dedicated Short Range Communications) last June, but NXP has recently launched Roadlink SAF5400 which it claims to be the world’s first “automotive qualified, high-performance single-chip DSRC modem” Key features for Roadlink SAF5400: Compliant with IEEE 802.11p, IEEE 1609.4 Compliant with: ETSI EN 302663 – Intelligent Transport Systems (ITS); Access layer specification for Intelligent Transport Systems operating in the 5 GHz frequency band ETSI EN 302571 – Intelligent Transport Systems (ITS); Radiocommunications equipment operating in the 5 855 MHz to 5 925 MHz frequency band; Harmonized EN covering the essential requirements of article 3.2 of the R&TTE Directive Compliant with ARIB T-109M – 700 MHz Band Intelligent Transport Systems Single channel handling for 802.11p reception/transmission. Includes Channel Switching Optional ECDSA verification: 2000 messages/sec (Brainpool/NIST curves 256 bits) Qualified in accordance with AEC-Q100 grade 2 Host […]
NXP i.MX RT Series Crossover Embedded Processor is Based on an ARM Cortex-M7 Core @ 600 MHz
Microcontrollers (MCUs) provide real-time processing, low power, low cost, and plenty of I/Os, but with security and user interface requirements of recent embedded devices, the processing power may be a limitation, and embedded systems designers may have to use an application processor instead gaining performance, but losing some of the benefits of MCUs. The bridge the gap between performance and usability, NXP has launched i.MX RT series of Crossover Embedded Processor which uses the powerful ARM Cortex-M7 MCU core clocked at up to 600 MHz, a frequency partially made possible by eliminating on-chip flash memory. The first member of the family is NXP i.MX RT1050 with the following key features and specifications: MCU Core – ARM Cortex-M7 @ up to 600 MHz; 3015 CoreMark / 1284 DMIPS Memory – Up to 512KB SRAM/TCM (Tighly Coupled Memory) with response time as low as 20 ns Storage – 96KB RAM; interfaces: NAND, […]
NXP Unveils LPC84x ARM Cortex M0+ MCU Family, and LPCXpresso845-MAX Evaluation Board
NXP Semiconductors has expanded LPC800 series MCUs with the new LPC84x family of 32-bit ARM Cortex-M0+ microcontroller said to offer 10 times the performance, three times more power saving savings, and 50 percent smaller code-size than 8- or 16-bit microcontrollers. Key features of LPC84x MCU family (LPC844 / LPC845): MCU Core – ARM Cortex-M0+ core @ 30 MHz with advanced power optimization RAM – 16 kB RAM (Logic for Bit banding across all of SRAM) Storage – 64 kB Flash, small 64-byte page size suitable for EEPROM emulation Peripherals Timers – 32-bit CTimer, WWDT, 4-channel multi-rate, SCTimer/PWM Serial Interfaces – Up to 4x I2C, 2x SPI, up to 5x UART Analog Interfaces – 12 ch, 12-bit ADC up to 1.2 Msps; 2x 10-bit DAC; comparator with external Vreg; 9-channel capacitive touch interface working in sleep and deep sleep modes Up to 54 GPIOs 25-ch DMA offloads core Power Control Five […]