neoverse

Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on Arm SystemReady SR-certified Ampere Altra Developer Platform launched for $3,999

Arm SystemReady SR-certified Ampere Altra Developer Platform launched for $3,999

Ampere Altra Developer Platform

ADLINK has just announced the availability of the Arm SystemReady SR-certified Ampere Altra Developer Platform equipped with the company’s COM-HPC Ampere Altra module with 32 to 80 64-bit Arm Neoverse N1 cores, 32GB to 128GB RAM. An adaptation to the earlier AVA Developer Platform expected to sell for $5,450, the Ampere Altra Developer Platform got a price cut to $3,999 at launch for a system with a 32-core processor, and 32GB DDR4. The system targets software developers wanting to build cloud-to-edge applications using standardized Arm hardware. Ampere Altra Developer Platform specifications: SoM – COM-HPC Ampere Altra module with Ampere Altra 32 to 80-core 64-bit Arm Neoverse N1 processor up to 1.7/2.2/2.6 GHz (32/64/80 cores, TPD: 60W to 175W), 32 GB to 128GB DDR4 ECC memory Storage – 128 GB NVMe M.2 SSD Mainboard – COM-HPC Server Base carrier board Video – VGA port Audio – 3.5mm audio jack Networking 1x […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 10 Comments on Arm Neoverse E1 & N1 Processors Target Edge and Cloud Infrastructure

Arm Neoverse E1 & N1 Processors Target Edge and Cloud Infrastructure

Neoverse E1

Arm has just announced two new processors for compute workloads with a power efficient Neoverse E1 platform targeting edge devices like 5G base stations, as well as the more powerful Neoverse N1 platform designed for the cloud, and aiming at challenging Intel Xeon processors. Arm Neoverse E1 Key specifications and features of Arm Neoverse E1: Simultaneous Multithreading (SMT) supporting two threads concurrently Up to 8 cores (16 threads) per cluster Superscalar, out-of-order pipeline Configurable private L2 cache Configurable L3 cache Low-latency Accelerator Coherency Port (ACP) for closely coupled accelerator integration Support cache stashing into L2/L3 cache Arm Neoverse E1 is the first Arm processor to support SMT and is best suited for data plane compute workloads such as 4G/5G transport, software-defined networking, software-defined storage, and SD-WAN. The platform features a scalable architecture suitable for 10Gb wireless/wireline devices to high-performance 100G+ Dataplane Processing Unit (DPU). Arm developed a 5G small cell […]

UP 7000 x86 SBC