The last RISC-V core announced by SiFive was the U8-Series out-of-order RISC-V Core IP that aims to compete against Arm Cortex-A72 Core. But in their latest announcement, the company built upon the 64-bit RISC-V U7-series with the SiFive Intelligence X280 multi-core, Linux capable RISC-V processor adding vector extensions and SiFive Intelligence Extensions, and optimized for AI/ML compute at the edge. SiFive Intelligence X280 key features: 64-bit RISC-V ISA with 8-stage dual-issue in-order pipeline, coherent multi-core, Linux capable based on U7 series core. SiFive Intelligence Extensions for ML workloads – BF16/FP16/FP32/FP64, int8 to 64 fixed-point data types 512-bit vector register length – Variable-length operations, up to 512-bits of data per cycle High-performance vector memory subsystem Memory parallelism provides cache miss tolerance Virtual memory support with precise exceptions Up to 48-bit addressing SiFive Intelligence includes software solutions to leverage the X280’s features and provide “great AI inference performance” using TensorFlow Lite. No […]
SiFive Intelligence X280 64-bit RISC-V processor integrates AI extensions
