mips News - Page 9 of 20 - CNX Software

December 20, 2018December 20, 2018 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Onion Omega2 Pro OpenWrt Linux IoT Board Comes with 8GB Storage (Crowdfunding)

Onion Omega2 and Omega2 Plus are MediaTek MT7688 MIPS based WiFi boards for IoT applications that were launched in 2016 for as low as $5. Both boards run OpenWrt (LEDE at the time), and Omega2 Plus included more memory and storage with respectively 128MB RAM, 32MB flash and a micro SD card. But Onion team found out that many users needed more storage space, and they’ve now come up with Omega2 Pro model with the same processor, 128MB RAM, and large 8GB flash considering we’re talking about a board running OpenWrt 18.06 here. Onion Omega2 Pro specifications: Wireless Module – Onion Omega2S+ with SoC – MediaTek MT7688 MIPS processor @ 580 MHz System Memory – 128MB DDR2 RAM Connectivity – 2.4 GHz 802.11 b/g/n Wi-Fi 4 Antenna – 2 dBi directional chip antenna (on mainboard) & u.FL connector for external antenna (on-module) Storage – 8 GB eMMC flash USB – […]

December 18, 2018 by Jean-Luc Aufranc (CNXSoft) - 12 Comments

Wave Computing to Open Source MIPS Architecture

There has been a lot of talks about RISC-V open source, royalty-free instructions set architecture this year, including the launch of RISC-V MCUs and Linux capable RISC-V processors, and corresponding development boards such as Hifive Unleashed. This even lead Arm to create a – now shutdown – microsite telling why people should stick with Arm instead of RISC-V. While RISC-V was clearly on the rise this year, MIPS architecture once a dominant players in routers and set-top box has been on the decline, even prompting Blu to write a guest review entitled “Baikal T1 MIPS Processor – The Last of the Mohicans?” hinting at the near extincsion of MIPS based solutions. But there may be hope, or at least a last ditch effort, with Wave Computing purchasing MIPS from Imagination Technology earlier this year, and now announcing the MIPS Open Initiative to effectively open source 32-bit and 64-bit MIPS ISA […]

October 23, 2018 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Linux 4.19 Release – Main Changes, Arm and MIPS Architectures

With Linus Torvalds taking a leave from the Linux kernel project, Greg Kroah-Hartman was the one to release Linux 4.19 last Sunday: Hi everyone! It’s been a long strange journey for this kernel release… While it was not the largest kernel release every by number of commits, it was larger than the last 3 releases, which is a non-trivial thing to do. After the original -rc1 bumps, things settled down on the code side and it looks like stuff came nicely together to make a solid kernel for everyone to use for a while. And given that this is going to be one of the “Long Term” kernels I end up maintaining for a few years, that’s good news for everyone. A small trickle of good bugfixes came in this week, showing that waiting an extra week was a wise choice. However odds are that linux-next is just bursting so […]

September 26, 2018September 28, 2018 by Jean-Luc Aufranc (CNXSoft) - 24 Comments

Baikal T1 MIPS Processor – The Last of the Mohicans?

CNXSoft: Guest post by Blu about Baikal T1 development board and SoC, potentially one of the last MIPS consumer grade platforms ever. It took me a long time to start writing this article, even though I had been poking at the test subject for months, and I felt during that time that there were findings worth sharing with fellow embedded devs. What was holding me back was the thought that I might be seeing one of the last consumer-grade specimen of a paramount ISA that once turned upside-down the CPU world. That thought was giving me mixed feelings of part sadness, part hesitation ‒ to not do some injustice to a possibly last-of-its-kind device. So it was with these feelings that I took to writing this article. But first, a short personal story. Two winters ago I was talking to a friend of mine over beers. We were discussing CPU […]

August 13, 2018August 13, 2018 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

Linux 4.18 Release – Main Changes, Arm and MIPS Architecture

Linus Torvalds has just announced the release of Linux 4.18: One week late(r) and here we are – 4.18 is out there. It was a very calm week, and arguably I could just have released on schedule last week, but we did have some minor updates. Mostly networking, but some vfs race fixes (mentioned in the rc8 announment as “pending”) and a couple of driver fixes (scsi, networking, i2c). Some other minor random things (arm crypto fix, parisc memory ordering fix). Shortlog appended for the (few) details. Some of these I was almost ready to just delay to until the next merge window, but they were marked for stable anyway, so it would just have caused more backporting. The vfs fixes are for old races that are really hard to hit (which is obviously why they are old and weren’t noticed earlier). Some of them _have_ been seen in real […]

June 6, 2018June 18, 2018 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Linux 4.17 Release – Main Changes, Arm & MIPS Architectures

Linus Torvalds released Linux 4.17 last Sunday: So this last week was pretty calm, even if the pattern of most of the stuff coming in on a Friday made it feel less so as the weekend approached. And while I would have liked even less changes, I really didn’t get the feeling that another week would help the release in any way, so here we are, with 4.17 released. No, I didn’t call it 5.0, even though all the git object count numerology was in place for that. It will happen in the not _too_distant future, and I’m told all the release scripts on kernel.org are ready for it, but I didn’t feel there was any real reason for it. I suspect that around 4.20 – which is I run out of fingers and toes to keep track of minor releases, and thus start getting mightily confused – I’ll switch […]

May 7, 2018May 7, 2018 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

MIPS I7200 Processor Core with nanoMIPS Architecture is Designed for LTE/5G Communications & Networking SoCs

MIPS has recently unveiled the I7200 multi-threaded multi-core processor for advanced LTE/5G communications and networking SoCs, which also happens to be the first MIPS core based on the new nanoMIPS 32-bit ISA. nanoMIPS is a variable instruction length ISA consisting of 16/32/48-bit instructions and various other optimizations that enables performance in the smallest code size. MIPS I7200 core features: 32-bit nanoMIPS Instruction Set Architecture with MIPS DSP ASE optimized instruction set extensions for integer DSP and 32-bit SIMD operations Balanced, 9-stage, dual-issue pipeline with Vertical Multi-Threading (VMT) Superscalar on a single thread per cycle Zero overhead context switching – can switch threads every clock cycle Implements MIPS MT ASE – can implement up to 3 fully OS visible Virtual Processor Elements (VPEs) per core, and up to 9 lightweight thread contexts (TCs) per core, assignable to the VPEs Configurable memory subsystem Support for caches, tightly coupled ScratchPad RAM (SPRAM), or […]

April 2, 2018April 3, 2018 by Jean-Luc Aufranc (CNXSoft) - No Comments

Linux 4.16 Release – Main Changes, Arm and MIPS Architectures

Linus Torvalds has just released Linux 4.16: So the take from final week of the 4.16 release looks a lot like rc7, in that about half of it is networking. If it wasn’t for that, it would all be very small and calm. We had a number of fixes and cleanups elsewhere, but none of it made me go “uhhuh, better let this soak for another week”. And davem didn’t think the networking was a reason to delay the release, so I’m not. End result: 4.16 is out, and the merge window for 4.17 is open and I’ll start doing pull requests tomorrow. Outside of networking, most of the last week was various arch fixlets (powerpc, arm, x86, arm64), some driver fixes (mainly scsi and rdma) and misc other noise (documentation, vm, perf). The appended shortlog gives an overview of the details (again, this is only the small stuff in […]