The SoC Discovery Kit is the latest addition to Microchip’s list of development kits for the PolarFire series. The series is the first SoC FPGA family powered by a deterministic, coherent RISC-V CPU cluster. They provide low power consumption, thermal efficiency, and defense-grade security for smart, networked systems. They also support a deterministic L2 memory system for Linux and real-time applications. Microchip launched the Icicle Kit for the PolarFire SoC in 2020 and it was followed by the Video and Imaging Kit which was intended for mid-bandwidth imaging and video applications. Now, Microchip has announced the Discovery Kit which is billed as a low-cost alternative to the Icicle. The Discovery Kit retains the full range of features needed for testing concepts quickly, developing firmware applications, and programming/debugging user code. According to Microchip, the kit will bring “a low-cost RISC-V and FPGA development for learning and rapid innovation” to new and […]
CERBERUS 2100 is a BASIC-programmable educational board with Z80 and 6502 8-bit CPUs
Olimex has just announced the launch of the CERBERUS 2100 open-source hardware, educational, multi-processor 8-bit computer with both Z80 and 6502 CPUs, as well as a Microchip AVR processor serving as an I/O controller. The CERBERUS 2100 features several CPLD and is fully programmable from the lowest level (individual gates and flip-flops) up to BASIC interpreters running on the Z80 and 6502 CPUs. Olimex did not design this themselves as the hardware design is from Bernardo Kastrup (aka TheByteAttic), while BASIC interpreters were written by Alexander Sharikhin (6502) and Dean Belfield (Z80). CERBERUS 2100 specifications: Processors Zilog Z80 8-bit microprocessor at 4 or 8 MHz (user selectable) Western Design Center W65C02S 8-bit microprocessor at 4 or 8 MHz (user selectable) “FAT-CAT” (Custom ATmega328pb) Microchip 8-bit AVR ATMega328PB microcontroller at 16 MHz CPLDs (ATF1508AS-7AX100) FAT-SCUNK (Scan CoUNter and clocK) and FAT-CAVIA (ChAracter Video Adapter) for video circuit connected to a 25.175 […]
Microchip introduces PIC16F13145 Series MCUs with customizable logic
Microchip recently introduced the PIC16F13145 series of 8-bit MCUs featuring a Configurable Logic Block (CLB). This allows users to create custom hardware-based logic functions within the MCU. This approach lowers the BOM costs and boosts performance. Last year, we saw Microchip introduce PIC32CZ Arm MCU with a Hardware Security Module (HSM) and before that, we saw they launched LAN8650/LAN8651 10BASE-T1S single-pair Ethernet Controllers. Feel free to check those out if you are interested in the topics. Microchip PIC16F13145 Series MCU Specification: 32MHz PIC16 CPU core Up to 1KB User SRAM for application data Up to 14KB Flash memory with code protection features CLB Capabilities: Up to 32 basic logic elements – AND/OR/NAND/NOR gates, buffers/inverting buffers, D/JK flip-flops, multiplexers, 4-input LUT Dynamic configuration for on-the-fly changes Tri-state logic capability Inputs/outputs from software, I/O pins, and PIC® peripherals (ADC, PWM, DAC, etc.) Less than 6 ns BLE propagation delay at 5.5V (typical) […]
Microchip PIC18-Q24 8-bit MCU focuses on security and supports Multi-Voltage I/O (MVIO)
The newly introduced Microchip PIC18-Q24 8-bit MCU implements security measures such as the Programming and Debugging Interface Disable (PDID) feature and optional support for an immutable bootloader, as well as support for Multi-Voltage I/O (MVIO) to interface with digital inputs or outputs at different operating voltages without the needs for level shifters. While it’s fun to find a new MCU platform that you can hack via serial, JTAG, or other debug interfaces, it can be a security issue, and the Microchip PIC18-Q24 aims to make that impossible by disabling programming and debugging interfaces and the 8-bit microcontroller also offers an option to make the bootloader impossible to modify once a specific configuration bit has been set. Microchip PIC18-Q24 key features and specifications: MCU core – 8-bit C compiler optimized RISC core @ up to 64 MHz Memory – Up to 4 KB of Data SRAM Memory Storage – Up to […]
Microchip PIC32CZ CA 300 MHz Arm Cortex-M7 MCU features a Hardware Security Module (HSM)
Microchip PIC32CZ CA is a new family of Arm Cortex-M7 microcontrollers with the PIC32CZ CA90 integrating a Hardware Security Module (HSM), and the PIC32CZ CA80 doing without one. The HSM in the PIC32CZ CA90 provides advanced security for industrial and consumer applications and operates as a secure subsystem with a separate MCU on board that runs the firmware and security features including hardware secure boot, key storage, cryptographic acceleration, true random number generator, and more. Microchip PIC32CZ CA key features and specifications: MCU core – Arm Cortex-M7 clocked at up to 300 MHz with 16KB ECC-protected instruction and data L1 cache, up to 256Kb of Tightly Coupled Memory (TCM): 128 KB each of ECC-protected Instruction and Data TCM Memory 512KB or 1MB SRAM with ECC, 8KB SRAM for backup mode 2MB, 4MB, or 8MB flash 2x 80KB boot flash memory 16-bit external bus interface (EBI) – Static memory controller for […]
Microchip PIC18-Q20 low-pin count MCU comes with up to two I3C interfaces
Microchip PIC18-Q20 is a new family of microcontrollers (MCUs) with a low-pin count (14 and 20-pin packages) that integrates up to two I3C interfaces as well as multi-voltage I/O (MVIO) interfaces. MIPI I3C was first teased in 2014, then officially announced in 2017, and the first MIPI I3C specification was released the following year, as a backward compatible update to I2C with lower power consumption, and higher bitrate allowing it to compete against SPI. We’ve seen it used in a few application processors and microcontrollers, but it’s the first time I3C can be found in a lower-cost, low-pin count microcontroller. Microchip PIC18-Q20 specifications: Core – PIC18 8-bit RISC microcontroller core @ 64 MHz Memory – 1KB to 4KB RAM Storage – 16KB to 64KB with Memory Access Partition (MAP) support, 256B EEPROM Peripherals Up to 2x I3C device interfaces Adhere to MIPI I3C Basic Specification 1.0 Support Target Reset Action […]
Snagboot is an open-source cross-vendor recovery tool for embedded targets
Bootlin has just released the Snagboot open-source recovery tool for embedded platforms designed to work with multiple vendors, and currently STMicro STM32MP1, Microchip SAMA5, NXP i.MX6/7/8, Texas Instruments AM335x and AM62x, and Allwinner “sunxi” processors are supported. Silicon vendors usually provide firmware flashing tools, some closed-source binaries, that only work with their hardware. So if you work on STM32MP1 you’d use STM32CubeProgrammer, while SAM-BA is the tool for Microchip processors, NXP i.MX SoC relies on UUU, and if you’ve ever worked on Allwinner processors you’re probably family with sunxi-fel. Bootlin aims to replace all those with the Snagboot recovery tool. The Python tool is comprised of two parts: snagrecover using vendor-specific ROM code mechanisms to initialize external RAM and run the bootloader (typically U-Boot) without modifying any non-volatile memories. snagflash communicates with the bootloader over USB to flash system images to non-volatile memories, using either DFU, USB Mass Storage, or […]
Microchip unveils Single Pair Ethernet (SPE) 10BASE-T1S and 100BASE-T1 Ethernet devices
Microchip has introduced a range of industrial-grade Single Pair Ethernet (SPE) devices for IIoT and industrial Operational Technology (OT) networks for low-speed Ethernet edge devices and a simplified cabling infrastructure for latency-sensitive applications. Microchip LAN8650/LAN8651 10BASE-T1S single pair Ethernet Controllers The LAN8650 and LAN8651 10BASE-T1S MAC-PHY Ethernet controllers come with an SPI for integration into basic microcontrollers rather than higher-end MCUs with a MAC. They can be used to connect sensors, actuators, and other devices over a simple twisted-pair cable. Microchip LAN8650/LAN8651 specifications: High-performance 10BASE‑T1S single-pair Ethernet PHY Compliant with IEEE Std. 802.3cg-2019 (10BASE-T1S) 10 Mbps over a single balanced pair of conductors Half-duplex point-to-point link segments up to at least 15m Half-duplex multidrop mixing segments up to at least 25m with up to at least 8 PHYs Integrated Media Access Controller (MAC) Host interface – SPI Supports time-sensitive networking (TSN) by timestamping frame ingress and egress EtherGREEN Energy Efficiency […]