fpga

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on Lattice Avant mid-range FPGA platform features up to 500K logic cells, 25 Gbps SERDES, Hard PCIe Gen4

Lattice Avant mid-range FPGA platform features up to 500K logic cells, 25 Gbps SERDES, Hard PCIe Gen4

Lattice Avant

Lattice Avant is a new low-power and small form factor mid-range FPGA platform, manufactured with a 16nm FinFET process, and equipped with 25 Gb/s SERDES, hardened PCI Express, external memory PHY interfaces, a high DSP count, and a security engine. Lattice Semi is better known for its entry-level FPGAs such as the iCE40 which is popular in the community thanks to low-cost hardware and support for open-source tools, but the Avant platform marks the company’s entry into the mid-range FPGA market, defined by chips with 100k to 500k logic cells (LCs). Lattice Avant highlights: FPGA fabric – 200K to 500K logic cells up to 350 MHz DSP – 700 to 1,8000 18×18 multipliers @ up to 650 MHz to support the latest AI algorithms Memory 14-36 Mbit embedded memory up to 650 MHz DDR3L/DDR4/LPDDR4 and DDR5 support I/Os 4x to 28x 25 Gbps multi-protocol SERDES Hard PCIe Gen4 200 to […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Innodisk EXMU-X261 FPGA Machine Vision Platform is based on AMD Xilinx Kria K26 SoM

Innodisk EXMU-X261 FPGA Machine Vision Platform is based on AMD Xilinx Kria K26 SoM

Innodisk EXMU-X261 FPGA machine vision platform

Innodisk, better known for its embedded storage and memory chips, had announced its intention to turn to the AI market earlier and started with the launch of USB camera modules last month, but the company has gone a step (or two, or three) further with the introduction of the EXMU-X261 FPGA machine vision platform. The EXMU-X261 is powered by an AMD Xilink Kria K26 system-on-module and features HDMI 1.4 video output, Gigabit Ethernet, four USB 3.1 Gen 1 ports for the cameras and other peripherals, as well as two M.2 sockets and a terminal block for expansion. EXMU-X261 specifications: System-on-module – AMD Xilinx Kria K26 FPGA module powered by a Zynq UltraScale+ XCK26 FPGA MPSoC with a quad-core Arm Cortex-A53 processor, up to 250 thousand logic cells, and a H.264/265 video encoder/decoder Storage – MicroSD card socket Video Output – HDMI 1.4 port Networking – Gigabit Ethernet RJ45 port USB […]

Posted on by Leo Zachary - 24 Comments on FNIRSI 1013D teardown and mini review – A portable oscilloscope based on Allwinner CPU & Anlogic FGPA

FNIRSI 1013D teardown and mini review – A portable oscilloscope based on Allwinner CPU & Anlogic FGPA

FNIRSI 1013D

The FNIRSI 1013D is a dual-channel flat-panel oscilloscope with a rich set of features. It is cost-effective and useful to people in the maintenance and R&D industries. Although it has been on the market for a few years, I purchased one, and I decided to introduce it and disassemble it to check out the hardware design. FNIRSI describes its oscilloscope as “small and portable”, so I assume it should include a lithium battery, a TFT LCD screen, a processor to handle the display, and another chip to process the digital signals. Let’s take it apart first to find out. FNIRSI 1013D oscilloscope unboxing FNIRSI 1013D package content: 1x FNIRSI 1013D oscilloscope 2x 100MHz matching probes (1X and 10X) 1x USB cable 1x Charging adapter 1x Instruction manual The FNIRSI 1013D adopts a 7-inch 800 x 480 resolution color TFT LCD with a capacitive touch screen. There are two input channels […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on AMD unveils low-cost Artix UltraScale+ AU7P FPGA and Zynq UltraScale+ ZU3T MPSoC

AMD unveils low-cost Artix UltraScale+ AU7P FPGA and Zynq UltraScale+ ZU3T MPSoC

AMD UltraScale AU7P FPGA UltraScale ZU3T MPSoC

AMD has added two new low-cost, low-power members to its UltraScale+ family with the Artix UltraScale+ AU7P FPGA and the Zynq UltraScale+ ZU3T MPSoC. Both devices are manufactured with the 16nm FinFET process and offer entry points to the transceiver-based UltraScale+ family with features such as high I/O-to-logic density, UltraRAM, DSP, and more. AMD Artix UltraScale+ AU7P FPGA The new AU7P FPGA is the smallest from the Artix UltraScale+ family with four 12.5Gbps transceivers, up to 82K system logic cells, 216 DSP slices, 4.9 Mbit RAM, and 248 I/Os. It is offered in a 10.5 x 8.5mm InFO package. The company says the chip provides up to 50% lower static power, 20% more I/O-to-logic ratio, and twice as many 3.3V HDIO compared to the AU10P device. The AU7P is designed for space-constrained and/or power-sensitive applications such as medical imaging, machine vision, professional cameras/monitors, and automotive radar/lidar. More details may be […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on System-on-module combines NXP i.MX 8M Mini Arm CPU and Xilinx Artix-7 FPGA

System-on-module combines NXP i.MX 8M Mini Arm CPU and Xilinx Artix-7 FPGA

NXP Arm + Xilinx FPGA development board

MYIR Tech has launched the MYC-JX8MMA7 system-on-module combining an NXP i.MX 8M Mini quad-core Arm Cortex-A53 processor with an AMD Xilinx XC7A25T Artix-7 FPGA. The 82 x 45mm CPU module comes with 2GB LPDDR4, 8GB eMMC flash, and 32MB QSPI Flash for the Arm processor and 256MB DDR3 and 32MB QSPI Flash for FPGA. It exposes I/Os through an MXM 3.0 edge connector and can operate in the industrial temperature range (-40 to 85°C). MYC-JX8MMA7 CPU module specifications: SoC – NXP i.MX 8M Mini with quad-core Cortex-A53 processor @ up to 1.6 (industrial) or 1.8 GHz, Cortex-M4F real-time core @ 400 MHz, Vivante GC320 and Vivante GCNanoUltra 3D/2D GPUs, 1080p60 H.265, H.264, VP8, VP9 video decoder, 1080p60 H.264 & VP8 video encoder FPGA – AMD Xilinx Artix-7 XC7A25T-2CSG325 with 23,360 logic cells, 3x GTP System Memory and Storage SoC – 2GB LPDDR4, 8GB eMMC flash, and 32MB QSPI Flash FPGA […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Zynq UltraScale+ SoM with up to 12GB RAM targets LiDAR applications

Zynq UltraScale+ SoM with up to 12GB RAM targets LiDAR applications

Zynq UltraScale+ SoM LiDAR

iWave Systems iW-RainboW-G30M is a system-on-module (SoM) based on AMD Xilinx Zynq UltraScale+ ZU4/ZU5/ZU7 FPGA MPSoC specially geared towards LiDAR applications for scientific and military applications. The module comes with up to 12GB of RAM, 4GB for the programmable logic (PL) and 8GB for the Arm Cortex-A53/R5-based Processing System (PS), two 240-pin high-density, high-speed connectors with 142 user I/Os, 16x GTH transceivers up to 16.3Gbps, and four GTR transceivers up to 6Gbps. iW-RainboW-G30M specifications: FPGA MPSoC  – AMD Xilinx Zynq Ultrascale+ ZU4, ZU5, or ZU7 MPSoC with Processing System (PS) featuring 2x or 4x Arm Cortex-A53 core @ 1.5 GHz, two Cortex-R5 cores @ 600MHz, H.264/H.265 Video Encoder/Decoder (VCU), ARM Mali-400MP2 GPU @ 677MHz, and Programming Logic (PL)/FPGA with up to 504K Logic cells & 230K LUTs System Memory 4GB DDR4 64-bit RAM with ECC for PS (upgradeable up to 8GB) 2GB DDR4 16-bit RAM for PL (upgradeable up to […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.0 Release

Linux 6.0 has just been released by Linus Torvalds: So, as is hopefully clear to everybody, the major version number change is more about me running out of fingers and toes than it is about any big fundamental changes. But of course there’s a lot of various changes in 6.0 – we’ve got over 15k non-merge commits in there in total, after all, and as such 6.0 is one of the bigger releases at least in numbers of commits in a while. The shortlog of changes below is only the last week since 6.0-rc7. A little bit of everything, although the diffstat is dominated by drm (mostly amd new chip support) and networking drivers. And this obviously means that tomorrow I’ll open the merge window for 6.1. Which – unlike 6.0 – has a number of fairly core new things lined up. But for now, please do give this most […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 13 Comments on 3D game running on FPGA shown to be 50x more efficient than on x86 hardware

3D game running on FPGA shown to be 50x more efficient than on x86 hardware

3D game FPGA

Sphery vs. shapes is an open-source 3D raytraced game written in C and translated into FPGA bitstream that runs 50 times more efficiently on FPGA hardware than on an AMD Ryzen processor. Verilog and VHDL languages typically used on FPGA are not well-suited to game development or other complex applications, so instead, Victor Suarez Rovere and Julian Kemmerer relied on Julian’s “PipelineC” C-like hardware description language (HDL) and Victor’s CflexHDL tool that include parser/generator and math types library in order to run the same code on PC with a standard compile, and on FPGA through a custom C to VHDL translator. More details about the game development and results are provided in a white paper. Some math functions were needed, including: floating point addition, subtraction, multiplication, division, reciprocals, square root, inverse square roots, vector dot products, vector normalization, etc. Fixed point counterparts were also used for performance reasons and to […]

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