fpga

Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on Fudan Micro JFM7K325T is a clone of AMD Embedded Kintex 7 325T FPGA

Fudan Micro JFM7K325T is a clone of AMD Embedded Kintex 7 325T FPGA

Kintex 7 325T FPGA clone board

Shanghai Fudan Microelectronics Group, also known as FMSH, has designed a clone of the AMD Embedded (previously Xilinx) Kintex 7 325T FPGA found in some boards and modules in mainland China. We are used to seeing clones or fakes of the STM32 microcontrollers, but somebody called “whatever” on Twitter noted a full-featured board based on a clone of the Kintex-7 325T FPGA with 326,080 LUTS and 16 transceivers. Twitter users were quick to point out the board was based on Fudan Micro JFM7K325T, and that it was indeed a clone of the Kintex 7 325T FPGA. The company describes itself as a “domestic leading company specializing in the design, development, production (testing), and system solution provision of super-large-scale integration”, but the company’s website does not have any information about the JFM7K325T chip. I could not find the board above online, but I still found MagicChips’ MC-JFM7K325T core board based on […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 10 Comments on uSDR – A tiny M.2 SDR board controllable from your web browser (Crowdfunding)

uSDR – A tiny M.2 SDR board controllable from your web browser (Crowdfunding)

uSDR M.2 SDR module

uSDR is an embedded software-defined radio (SDR) M.2 board based on an AMD Embedded Artix-7 FPGA and designed to be controlled in the Chrome, Opera, or Edge browser without specific drivers or software thanks to WebUSB technology. The module can be inserted into any compatible host, or through M.2, USB, mini PCIe or PCIe adapters, and used from a web browser with ready-to-use applications such as a spectrum monitor or a signal analyzer, or your own JavaScript, C/C++, Rust, Go, or C# application thanks to WebAssembly and the Emscripten project. uSDR specifications: RFIC – Lime Microsystems LMS6002D programmable RF (FPRF) transceiver IC operates from 300MHz to 3.8GHz FPGA – AMD Embedded XC7A35T (Artix-7) FPGA with 33,280 logic cells Full-duplex TX & RX Frequency range – 300 – 3700 MHz (usable range typically starts from 230 MHz) RX/TX Bandwidth – 0.75 – 28 MHz plus bypass mode Clock generator – SI5332A […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Pico-Ice board combines Raspberry Pi RP2040 MCU with Lattice ICE40 UltraPlus 5K FPGA

Pico-Ice board combines Raspberry Pi RP2040 MCU with Lattice ICE40 UltraPlus 5K FPGA

Pico Ice Raspberry Pi RP2040 Lattice FPGA board

tinyVision.ai Pico-Ice is a development board with a Raspberry Pi RP2040 MCU and a Lattice ICE40 UltraPlus 5K FPGA connected through an 8-bit bus. The Arm Cortex-M0+ microcontroller provides the clock for the FPGA and can program the FPGA directly or the dedicated FPGA flash using a drag-drop of a UF2 file. Just a few days ago we wrote about the LILYGO T-FPGA board that combines an ESP32-S3 wireless MCU with a Gowin FPGA connected through a 6-bit bus, and the Pico-Ice board provides a similar option with different chips and without wireless connectivity. Pico-Ice specifications: MCU – Raspberry Pi RP2040 dual-core Cortex-M0+ microcontroller @ 133 MHz with 264KB SRAM with all pins exposed FPGA – Lattice UltraPlus iCE40UP5K FPGA with 5.3K LUTs, 1Mbit SPRAM, 120Kbit DPRAM, 8x multipliers with all pins brought out Memory & storage chips MCU – 4MB QSPI flash FPGA – 4MB QSPI Flash, 8MB low […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on LILYGO T-FPGA devkit combines ESP32-S3 WiSoC with Gowin GW1NSR-4C FPGA

LILYGO T-FPGA devkit combines ESP32-S3 WiSoC with Gowin GW1NSR-4C FPGA

ESP32-S3 Gowin FPGA devkit

LILYGO T-FPGA development kit is comprised of an M.2 module with an ESP32-S3 WiFi and Bluetooth wireless microcontroller and a Gowin GW1NSR-4C FPGA with 4,608 LUTs, and a carrier board that gives easy access to I/Os and comes with a 18650 battery holder. The module comes with a USB -C OTG port connected to the ESP32-S3, and a USB-C FPGA port for the FPGA. The “T-FPGA shield” carrier board includes four Pmod interfaces and a STEMMA Qt/Qwiic connector for expansion, plus several pins for 3.3 and GND, and another 20-pin I/O header. LILYGO T-FPGA specifications: Wireless MCU – Espressif Systems ESP32-S3R8 dual-core Tensilica LX7 @ up to 240 MHz with vector instructions for AI acceleration, 512KB RAM, 8MB PSRAM, wireless connectivity Storage – 16MB flash FPGA – Gowin Semiconductors GW1NSR-LV4CQN48PC6/I5 with 4,608 LUT4, 256Kb flash, 64Mb PSRAM, 64Mb Hyperflash, 32Mb NOR flash Connectivity via ESP32-S3 2.4 GHz 802.11 b/g/n Wi-Fi […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 24 Comments on $25 Sipeed Tang Nano 20K FPGA board can simulate a RISC-V core, run Linux, retro games

$25 Sipeed Tang Nano 20K FPGA board can simulate a RISC-V core, run Linux, retro games

Sipeed Tang Nano 20K

The Sipeed Tang Nano 20K is a low-cost FPGA development board based on Gowin GW2AR-18 FPGA with 20,736 logic cells and 64Mbit RAM, which coupled with  64MBit QSPI flash provides enough resources to simulate a 32-bit RISC-V core booting Linux or playing retro games in an emulator. The FPGA board comes with a USB-C port for power and to load the FPGA bitstream through a BL616 microcontroller that also acts as a USB to serial chip, an HDMI port and an RGB LCD interface for video output, two user buttons, and two rows GPIOs to connect peripherals such as gamepads (through adapters). Sipeed Tang Nano 20K specifications: FPGA – Gowin GW2A-LV18QN88C8I7 with 20,736 logic units (LUT4) 15,552 flip-flops (FF) RAM 41,472 shadow SRAM (S-SRAM) 828K block SRAM (B-SRAM) Numbers of B-SRAM – 46 64Mbit 32-bit SDR SDRAM 48x 18×18 multipliers 2x PLLs 8x I/O Bank Onboard debugger – Bouffalo Labs […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on AMD Versal AI Edge SoC FPGA system-on-module targets ADAS, robotics, medical imaging, and other AI applications

AMD Versal AI Edge SoC FPGA system-on-module targets ADAS, robotics, medical imaging, and other AI applications

AMD Xilinx Versal AI Edge System-on-Module

iWave Systems iW-Rainbow-G57M is a system-on-module (SoM) based on the AMD (Xilinx) Versal AI Edge series of Cortex-A72/R5 SoC FPGAs designed to deliver AI acceleration at relatively low power for demanding applications such as ADAS, robotics, and medical imaging. The module comes with up to 8GB 64-bit LPDDR4, 16GB eMMC Flash, 256MB QSPI Flash, delivers up to 45 TOPS of AI performance, and features eight transceivers that can be used for high-speed Ethernet, PCIe, MIPI DSI/CSI interfaces, and/or others as required by the customer’s specific project. iW-Rainbow-G57M specifications: FPGA SoC – AMD Xilinx Versal AI Edge/Prime SFVA784 package (VE2302, VE2202, VE2102,  or VE2002) with Dual Arm Cortex-A72 core processor @ up to 1.6 GHz Dual-core Arm Cortex-R5F Up to 328K Logic cells & 150K LUTs Programmable Network on Chip (NoC) Up to 45 TOPS (INT4) AI compute 8x GTYP Transceivers @ 28.21 Gbps (VE2302 & VE2202 only) Memory – Up […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 15 Comments on Cologne GateMate A1 FPGA chip with 20,480 LE is programmable with an open-source toolchain

Cologne GateMate A1 FPGA chip with 20,480 LE is programmable with an open-source toolchain

GateMate A1 FPGA development board

Cologne Chip GateMate A1 is an FPGA with 20,480 logic elements best suited for lower-power applications and programmable with an open-source toolchain based on nMigen, Yosys, and other open-source tools. The A1 FPGA also comes with 1,280 Kbit block SRAM, four PLLs, a quad SPI interface up to 100 MHz, a 5Gbps SerDes interface, and the company offers an evaluation board to get started with development. GateMate A1 specifications: CPE Architecture 20,480 programmable elements (CPE) for combinatorial and sequential logic 40,960 Latches / Flip-Flops within programmable elements CPE consists of LUT-tree with 8 inputs Each CPE is configurable as a 2-bit full-adder or 2×2-bit multipliers Features 4x programmable PLLs quad SPI interface up to 100 MHz 1,280 Kbit dual-ported block RAM with variable data widths in 32 x 40 Kbit RAM cells Multipliers with arbitrary size implementable in CPE array Multiple clocking schemas All 162 GPIOs are configurable as single-ended […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Linux 6.3 release – Notable changes, Arm, RISC-V and MIPS architectures

Linux 6.3 release – Notable changes, Arm, RISC-V and MIPS architectures

Linux 6.3 release

Linux Torvalds has just announced the release of Linux 6.3 on the Linux Kernel Mailing List (LKML): It’s been a calm release this time around, and the last week was really no different. So here we are, right on schedule, with the 6.3 release out and ready for your enjoyment. That doesn’t mean that something nasty couldn’t have been lurking all these weeks, of course, but let’s just take things at face value and hope it all means that everything is fine, and it really was a nice controlled release cycle. It happens. This also obviously means the merge window for 6.4 will open tomorrow. I already have two dozen pull requests waiting for me to start doing my pulls, and I appreciate it. I expect I’ll have even more when I wake up tomorrow. But in the meantime, let’s enjoy (and test) the 6.3 release. As always, the shortlog […]

UP 7000 x86 SBC