fpga News - Page 25 of 34 - CNX Software

June 14, 2017 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

$89 MiniZed Development Board based on Xilinx Zynq Z-7007S SoC Includes WiFi, Bluetooth, Arduino Headers

Avnet has unveiled MiniZed development board – part of ZedBoard family – powered by a Xilinx Zynq Z-7007s SoC with an ARM Cortex A9 processor and FPGA fabric, supporting WiFi and Bluetooth connectivity, and equipped with Arduino and PMOD headers. MiniZed board (AES-MINIZED-7Z007-G) specifications: SoC – Xilinx Zynq-7007S single ARM Cortex A9 processor up to 677 MHz + FPGA with 23K logic cells, 1.8 Mb block RAM, 60 DSP slices System Memory – 512 MB DDR3L Storage – 8 GB eMMC flash, 128 Mbit QSPI flash Connectivity – Wi-Fi 802.11b/g/n and Bluetooth 4.1 plus EDR and BLE via Murata “Type 1DX” wireless module USB – 1x USB 2.0 host port Sensors – 3-axis accelerator and temperature sensor (LIS2DS12); Digital Microphone (MP34DT05) Expansion Interfaces: 2x Pmod compatible connectors with 16x GPIOs Arduino UNO R3 compatible header with 22x GPIOs Debugging – JTAG and serial console via micro USB port Misc – 2x […]

May 29, 2017 by Jean-Luc Aufranc (CNXSoft) - No Comments

Intel DLIA is a PCIe Card Powered by Aria 10 FPGA for Deep Learning Applications

Intel has just launched their DLIA (Deep Learning Inference Accelerator) PCIe card powered by Intel Aria 10 FPGA, aiming at accelerating CNN (convolutional neural network) workloads such as image recognition and more, and lowering power consumption. Some of Intel DLIA hardware specifications: FPGA – Intel (previously Altera) Aria 10 FPGA @ 275 MHz delivering up to 1.5 TFLOPS System Memory – 2 banks 4G 64-bit DDR4 PCIe – Gen3 x16 host interface; x8 electrical; x16 power & mechanical Form Factor – Full-length, full-height, single wide PCIe card Operating Temperature – 0 to 85 °C TDP – 50-75Watts hence the two cooling fans The card is supported in CentOS 7.2, and relies on Intel Caffe framework, Math Kernel library for Deep Neural Networks (MKL-DNN), and works with various network topologies (AlexNet, GoogleNet, CaffeNet, LeNet, VGG-16, SqueezeNet…). The FPGA is pre-programmed with Intel Deep Learning Accelerator IP (DLA IP). Intel DLIA can […]

May 25, 2017May 25, 2017 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Melon S3 FPGA Arduino & Raspberry Pi Compatible Board is Programmable over WiFi using ESP8266 WiSoC

Q-Wave Systems, an embedded systems company based in Thailand, has designed Melon S3 FPGA board powered by a Xilinx Spartan 3E FPGA with WiFi connectivity added through a ESP8266 module programmable with the Arduino IDE , and featuring two Raspberry Pi compatible headers. The FPGA bitstream can be updated over WiFi, and does not require a JTAG debugger. Melon S3 FPGA specifications: FPGA – Xilinx Spartan XC3S500E FPGA with 500K gates, 73Kb Distributed RAM, 4 Digital Clock Manager (DCM), 20 Multipliers (18×18), 360 Kb Block RAM WiFi module – WROOM-2 with Espressif ESP8266 32-bit MCU @ 80 MHz supporting 802.11 b/g/n WiFi. Storage – 4MB SPI flash in total with 1MB for ESP8266, 3 MB for FPGA Expansion – 2x 40-pin Raspberry Pi compatible headers; 3.3V tolerant Debugging – Onboard USB-UART Silicon Labs CP2104 for configuration, debugging and power; 6-pin JTAG port for debugging/programming Misc – 8x Users LEDs, 4x […]

May 10, 2017 by Jean-Luc Aufranc (CNXSoft) - 19 Comments

Meet Zynqberry, a Xilinx Zynq FPGA Board with Raspberry Pi 2/3 Form Factor

Earlier this year, I wrote about Trenz Electronic’s Xilinx Zynq Ultrascale+ system-on-module, but I’ve just found out I missed another interesting product from the company. The ZynqBerry is a board powered by Zilinx Zync Z-7007S or Z-7010 ARM + FPGA SoC with Raspberry Pi 2/3 form factor. ZynqBerry specifications: SoC Xilinx Zynq XC7Z007S-1CLG225C (Z-7007S) single core ARM Cortex-A9 MPCore up to 766MHz + FPGA with 23K logic cells Xilinx Zynq XC7Z010-1CLG225C (Z-7010) dual core ARM Cortex-A9 MPCore up to 866 MHz + FPGA with 28K logic cells System Memory – 128 or 512 MB DDR3L Storage – 16 MB Flash SPI flash + micro SD card slot Video Output – HDMI, MIPI DSI interface Audio Output – HDMI, 3.5mm audio jack (PWM audio only) Connectivity – 100 MBit Ethernet via (LAN9514 USB Hub with Ethernet USB – 4x USB 2.0 host ports Camera – MIPI CSI-2 interface Expansion – 40-pin Raspberry […]

May 10, 2017 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Christmann RECS|Box Atlas Quad Apalis Microserver Evaluation Kit Supports Four Toradex Apalis SoM

System-on-modules are normally used in low volume embedded systems, but they can also be used in microservers, for example to upgrade capacity as needed. Christmann informationstechnik + medien GmbH has developed a microserver evaluation kit taking up to 4 Toradex Apalis SoMs for example based on Nvidia Tegra K1 processor, and also offers full rack systems with up to 72 modules. Christmann RECS|Box Atlas Quad Apalis specifications: Modules – 4x Slots for Apalis SoM Connectivity – 1 GBit/s Compute Ethernet, 1 GBit/s Management Ethernet Video Output – 1x HDMI USB – 3x USB host ports, 1x micro USB port Misc – 5 Status LEDs for USB, communication, and serial console, 4x fan connectors, KWM switch, 5x temperature sensors, 6x current sensors, 1x voltage monitor, fan speed monitoring Power Supply – 12V via a 4-pin jack Dimensions – 300 x 145 x 68 mm The evaluation kit includes an Atlas board […]

May 5, 2017 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

SiFive Launches 32-bit E31 Coreplex & 64-bit E51 Coreplex RISC-V Processors, Reveals Pricing

SiFive unveiled their Freedom U500 and E500 open source RISC-V SoCs last year, and a little layer launched HiFive1 Arduino compatible development board based on SiFive Freedom E310 processor. The company has now launched their non-open source Coreplex IP also based on RISC-V ISA with the 32-bit E31 Coreplex and 64-bit E51 Coreplex, and explained details about pricing. Some of the key features of the processors are listed below: E31 Coreplex 32-bit RV32IMAC core @ 900 to 1.5 GHz (with 28nm process) Advanced Memory Subsystem – 16KB, 2-way Instruction Cache, Instruction Tightly Integrated Memory (ITIM) option, up to 64KB Data Tightly Integrated Memory (DTIM) support Up to 16 local interrupts with vectored addresses Performance – 1.61 DMIPS/MHz ; 2.73 Coremark/MHz Power Consumption 28nm HPC process – Core only: 150 DMIPS/mW ; Coreplex: 41 DMIPS/mW 55nm LP process – Core only: 95 DMIPS/mW; Coreplex: 16 DMIPS/mW Applications: Edge Computing, Smart IoT […]

May 2, 2017May 3, 2017 by Jean-Luc Aufranc (CNXSoft) - 12 Comments

ZX Spectrum Next Retro Keyboard PC Relies on Xilinx FPGA, Raspberry Pi Zero “Accelerator” Board (Crowdfunding)

ZX Spectrum keyboard computer was launched in April 1982 in the United Kingdom, and 35 years later, a team of developers has now been working on ZX Spectrum Next somewhat resuscitating ZX Spectrum by emulating Z80 processor in a Xilinx FPGA, using an optional Raspberry Pi Zero board as an accelerator, and adding some modern features like HDMI output and WiFi. While the case is only a 3D rendering for now, they have a working board prototype with the following specifications: FPGA – Xilinx Spartan-6 FGPA emulating Z80 processor in 3.5Mhz and 7Mhz modes System Memory – 512KB RAM (expandable to 1.5MB internally and 2.5MB externally) Storage – SD Card slot, with DivMMC compatible protocol used in the original ZX Spectrum Video Hardware sprites, 256 colours mode, Timex 8×1 mode etc. Output: RGB, VGA, HDMI Audio – 3x AY-3-8912 audio chips with stereo output + FM sound Networking – Optional […]

April 5, 2017 by Jean-Luc Aufranc (CNXSoft) - No Comments

Embedded Systems Conference 2017 Schedule – May 3-4

The Embedded Systems Conference 2017 will take place over two days in Boston, US on May 3-4, and the organizers have published the schedule of the event. Even if you’re not going to attend, you’ll often learn something or find new information by just checking out the talks and abstracts, so I’ve created my own virtual schedule with some of the most interesting sessions. Wednesday, May 3rd 08:00 – 08:45 – Combining OpenCV and High Level Synthesis to Accelerate your FPGA / SoC EV Application by Adam Taylor, Adiuvo Engineering & Training Ltd This session will demonstrate how you can combine commonly used Open source frameworks such as OpenCV with High Level Synthesis to generate a embedded vision system using FPGA / SoC. The combination of OpenCV and HLS allows for a much faster algorithm development time and consequently a faster time to market for the end application. 09:00 – 09:45 […]