fpga News - Page 16 of 33 - CNX Software

June 24, 2020 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

Sipeed TANG Hex is a Low-Cost Xilinx Zynq-7020 Arm FPGA Board

Last year, Sipeed launched a $5 FPGA board called Sipeed Tang and based on an entry-level Gowin GW1N-1-LV FPGA. But I had not noticed the company had also worked on a more powerful, yet still low-cost Xilinx Zynq-7020 board in a business card form factor not too dissimilar from the Raspberry Pi model B form factor. Meet Sipeed TANG Hex. So far a low-cost Zynq-7010 or Zynq-7020 board met you had to spend $99 to $199 with products such as MyIR Z-Turn and Digilent PYNQ-Z1. But Sipeed Tang HEX can be purchased for as little as $73 shipping on Aliexpress, or 439 RMB ($62) on Taobao for people based in mainland China. It might be tempting to get a low-cost board to get started, but is it worth it? Read on to find out. Sipeed TANG Hex specifications: SoC – Xilinx Zynq-7020 (XC7Z020-1CLG484) dual-core Arm Cortex-A9 processor and FPGA with […]

June 22, 2020April 30, 2021 by Jean-Luc Aufranc (CNXSoft) - No Comments

zGlue Launches the Open Chiplet Initiative in Collaboration with Google and Antmicro

We first covered zGlue’s ZiP (zGlue Integration Platform) in 2018 as the company introduced its multi-chip module similar to SiP (system-in-package) via a crowdfunding campaign. Just like SiP, the technology packages several components into a single package, but costs have been brought down to enable low-volume production of custom chips for a reasonable price. Since then the company announced new ZiP multi-chip modules such as nRF52832 based Omnichip and the FPGA, Arm or/and RISC-V based GEM ASIC by Antmicro. The company recently announced the Open Chiplet Initiative, a collection of open-source designs, tools and file formats, launched in collaboration with Google and Antmicro. There are four main types of tools within the Open Chiplet Initiative: Open Chiplet Interfaces – Currently only ZEF (zGlue Chiplet Info Exchange Format) is provided. It defined the part numbers, pins, and mechanical dimensions of various parts. The ZEF specification can be found on Github. Design […]

June 9, 2020June 9, 2020 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Exor GigaSOM GS01 SoM and Devkit Combine Intel Atom E39xx CPU and Cyclone 10 GX FPGA

EXOR Intel Atom + Cyclone FPGA Smart Factory / Industrie 4.0 Development Kit

EXOR International has worked in collaboration with Arrow Electronics to design and manufacture GigaSOM GS01 system-on-module combining an Intel Atom E39xx Apollo Lake processor and Cyclone 10 GX FPGA. The module and corresponding development kit are specifically designed for smart factory & “Industrie 4.0” applications with the processor running Intel’s time-coordinated computing plus a real-time “IoT stack”, and the FPGA supporting IEEE 802.1 time-sensitive networking (TSN) and 10Gbps connectivity. GigaSOM GS01 module specifications: Apollo Lake SoC (one or the other) Intel Atom x5-E3930 dual-core processor @ 1.3 GHz / 1.8 GHz (Turbo) with 12EU Intel HD Graphics 500; 6.5W TDP Intel Atom x5-E3940 quad-core processor @ 1.6 GHz / 1.8 GHz with 12EU Intel HD Graphics 500; 9.5W TDP Intel Atom x7-E3950 quad-core processor @ 1.6 GHz / 2.0 GHz with 18EU Intel HD Graphics 505; 12W TDP FPGA – Intel Cyclone 10 GX up to 220 KLE System Memory […]

June 6, 2020June 6, 2020 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Efinix Releases Three RISC-V Software-Defined SoC’s Optimized for Trion FPGA’s

Efinix has announced three RISC-V Software-defined SoC’s based on Charles Papon’s VexRiscv core and optimized for the company’s Trion T8 to T120 FPGA’s. VexRiscv is a 32-bit RISC-V CPU using RISCV32I ISA with M and C extensions, has five pipeline stages (fetch, decode, execute, memory, and writeback), and a configurable feature set. Each SoC includes a RISC-V core, memory, as well as various I/O and interfaces. Key features for each of three RISC-V SoC’s: Ruby SoC FPGA footprint – ~12K LEs/78 RAM blocks Performance – 50 MHz (1.16 DMIPS/MHz) Memory – 4 KB on-chip RAM, up to 3.5 GB DDR DRAM Peripherals – 16x GPIO, Timer, PLIC, 3x SPI masters, 3x I2C masters/slaves, 2x UARTs 1x AXI4, 2x APB3 user peripherals Target applications – real-time system controls and image signal processing. Jade SoC FPGA footprint – ~7K LEs/93 RAM blocks Performance – 50 MHz (1.2 DMIPS/MHz) Memory – 32 KB […]

May 11, 2020 by Jean-Luc Aufranc (CNXSoft) - No Comments

4K Vision Edge Computing Platform Features Xilinx Zynq UltraScale+ ZU3EG MPSoC

Last year, MyIR Tech introduced MYD-CZU3EG development board powered by a Xilinx Zynq UltraScale+ ZU3EG MPSoC with Arm Cortex-A53 cores and FPGA fabric designed for applications such as cloud computing, machine vision, flight navigation, and other complex embedded applications. The company has now announced another Zynq Ultrascale+ ZU3EG based platform dedicated to machine vision. The VECP Starter Kit (Vision Edge Computing Platform) is comprised of MYD-CZU3EG-ISP development board fitted with the company’s MYC-CZU3EG Zynq UltraScale+ MPSoC CPU module, a fansink, and a SONY IMX334 4K camera sensor. MYD-CZU3EG-ISP development board specification: MYC-CZU3EG SoM MPSoC – Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784E (ZU3EG, 784 Pin Package) MPSoC with quad-core Arm Cortex-A53 processor @ 1.2 GHz, dual-core Cortex-R5 processor @ 600 MHz, Arm Mali-400MP2 GPU, and 16nm FinFET+ FPGA fabric (154K logic cells, 7.6 Mb memory, 728 DSP slices) System Memory – 4GB DDR4 @ 2,400MHz Storage – 4GB eMMC Flash, 128MB QSPI Flash […]

March 15, 2020March 15, 2020 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

Radiona ULX3S Open Source Hardware ECP5 FPGA Development Board Launched for $99 and Up (Crowdfunding)

ULX3S Lattice ECP5 FPGA Educational Board

Last summer, we wrote about Radiona ULX3S education board combining a Lattice Semi ECP5 FPGA with an Espressif Systems ESP32 WiFi & Bluetooth WiSoC. Designed for a digital logic course at the University of Zagreb, the board is open-source hardware with KiCAD hardware design files released on GitHub, and programmable with the Arduino IDE (FPGArduino) and ProjectTrellis open-source toolchain. At the time, there was only a version based on Lattice ECP5 85F with 84K LUT, but they’ve now made versions with cheaper variants of ECP5 FPGA and launched the board on Crowd Supply. Radiona ULX3S specifications: FPGA (one of the other) Lattice ECP5 LFE5U-85F-6BG381C with 84K LUT Lattice ECP5 LFE5U-45F-6BG381C with 44K LUT Lattice ECP5 LFE5U-12F-6BG381C with 12K LUT System Memory – 32MB SDRAM @ 166 MHz Storage – 4–16MB Quad-SPI Flash for FPGA config and user data storage; MicroSD slot Audio – 3.5 mm jack with 4 contacts (analog […]

February 7, 2020February 7, 2020 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Register to the Embedded Online Conference for Free Before February 29th

Events such as the Embedded Linux Conference and Embedded Systems Conference take place in the US and Europe every year. There are plenty of talks and it’s certainly good for networking, but you need to travel to the event and the entrance fee to have access to all session costs several hundred dollars if you book early, and over one thousand dollars if you register close to the date of the event. Most ELC/ELCE videos usually end up on The Linux Foundation YouTube channel, but the Beningo Embedded Group and Embedded Related website decided to organize a similar conference happening online and simply called the “Embedded Online Conference“. The conference offers topics about embedded systems, DSP, machine learning and FPGA and will take place on May 20. There are currently 17 talks, but they are still calling for talks so more sessions may be added before the actual event. You’ll […]

January 26, 2020January 26, 2020 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC’s with Accelerators

FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled “Open ESP – The Heterogeneous Open-Source Platform for Developing RISC-V Systems” with an excerpt of the abstract reading: ESP is an open-source research platform for RISC-V systems-on-chip that integrates many hardware accelerators. ESP provides a vertically integrated design flow from software development and hardware integration to full-system prototyping on FPGA. For application developers, it offers domain-specific automated solutions to synthesize new accelerators for their software and map it onto the heterogeneous SoC architecture. For hardware engineers, it offers automated solutions to integrate their accelerator designs into the complete SoC. If we go to the official website, we can see ESP (Embedded Scalable Platform) actually supports both 32-bit Leon3 (Sparc) and 64-bit Ariane (RISC-V) cores, and various hardware accelerators from the platform or third parties. Highlights: […]