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June 13, 2014June 13, 2014 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Marvell Armada 370 Processor Datasheet Released, Mainline Linux Kernel Supported on Netgear ReadyNAS 102/104

Free Electrons has been working on porting several ARM SoC to the Linux kernel (mainline), including Marvell XP and 370 SoCs, and they’ve been informed by Marvell that the company finally released Marvell Armada 370 processor publicly without requiring NDA nor registration. Marvell Armada XP dual and quad core processors datasheet found in higher-end NAS and cloud servers has not been released (yet), but we’ve been told many peripheral blocks are very similar, so Marvell Armada 370 datasheet can also be used for Armada XP processors to some extend. Two documents have actually been released for Marvell Armada 370: the functional specification and the hardware specification (datasheet). The first document is actually the one with the most information with 1148 pages providing details about peripherals, against 164 pages for the latter providing details about pins and electrical characteristics. So we’ve got an ARM SoC with mainline kernel support, and decent […]

June 11, 2014May 29, 2017 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Linux 3.15 Released

Linus Torvalds announced the release of Linux Kernel 3.15 last Sunday: So I ended up doing an rc8 because I was a bit worried about some last-minute dcache fixes, but it turns out that nobody seemed to even notice those. We did have other issues during the week, though, so it was just as well. The futex fixes and cleanups may stand out, but as usual there’s various other random fixes since rc8 in there too: mainly drivers (drm, networking, sound, usb etc), networking, scheduling and perf tooling. But it’s all been fairly small and quiet, which *may* of course be due to the fact that last week was also the first week of the merge window for 3.16. That might have distracted some developers. I’m not entirely convinced I liked the overlap, but it seemed to work ok, and unless people scream really loudly (“Please don’t _ever_ do that again”) and give good […]

June 5, 2014June 5, 2014 by Jean-Luc Aufranc (CNXSoft) - No Comments

First Tizen 3.0 Common Milestone Released, Developer Program Announced

The Tizen Steering Group has announced the first release of Tizen 3.0 Common. Tizen Common is the common subset of development / build / test platform of the Tizen profiles, used by platform developers to develop the next version of the profiles, and a Tizen 3.0 common release is planned every quarter. This milestone release includes: 64-bit support for both Intel and ARM architectures Crosswalk-based web runtime Multiuser support Systemd Security: three-domain rule system for SMACK and Cynara as authorization framework Wayland display server Pre-built binary releases for can be downloaded @ http://download.tizen.org/releases/daily/tizen/common/common-wayland-x86_64/tizen_20140602.26/ for Intel Atom 3815 NUC Kit and NEXCOM VTC1010 in-vehicle computer based on Intel Atom 3825. However, Tizen 3.0 Common will also be tested on Intel NUC Haswell (core i5), Lenovo x230 IvyBridge (core i5) and on the ARM side, ODROID-U3 development board. If you want to build your own, refer to the developer guide, using tizen_common_2014.Q2 tag. More details can be found […]

June 4, 2014June 7, 2014 by Jean-Luc Aufranc (CNXSoft) - 8 Comments

Cavium ThunderX Server SoC Features up to 48 ARM 64-bit Cores

ARM SBSA specification for server supports up to 268,435,456 CPU cores for the second level of standardization on one or a combination of SoCs. We’re not quite up there just yet, but Cavium ThunderX is an ARM server SoC with up to 48 cores on a single chip, which is the highest number of cores I’ve ever heard of in an ARM SoC. The company created their own custom processor cores using an ARMv8 architecture license, designing an SoC complies with ARM’s Server Base System Architecture (SBSA) standard with the following key features: ARM based SoC that scales up from 8 to 48 cores with up to 2.5 GHz core frequency with 78K I-Cache, 32K D-Cache, and 16MB L2 cache. Fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI) Integrated I/O capacity with 100s of Gigabits of I/O bandwidth 4x DDR3/4 72-bit memory controllers supporting up to 1TB RAM […]

May 30, 2014 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

Linaro 14.05 Released with Linux Kernel 3.15, Android 4.4.2, and Ubuntu Trusty

Linaro 14.05 has been released with Linux Kernel 3.15-rc5 (baseline), Linux Kernel 3.10.40 (LSK), Android 4.4.2, and Ubuntu has been switched from Saucy to Trusty. More work has been done on big.LITTLE processing and ARMv8 support with notably completing bootstrapping with Debian 64-bit. New hardware platform have started to pop-up such as TI J6-Vayu which must be an evaluation board for Texas Instruments Jacinto 6 dual core Cortex A15 SoC for automotive application, as well as IFC6410, a Snapdragon 600 development board which got a Ubuntu LEB image. This month also marks the first release of Linaro GCC 4.9 toolchain. Here are the highlights of this release: Linux Linaro 3.15-rc5-2014.05 new Android topic (linaro-android-3.15-experimental) uses the resent AOSP code base GATOR version 5.18 (same version as in 2014.04) uprobes topic removed as all patches have been accepted into mainline updated big-LITTLE-pmu topic from ARM LT updated basic Capri board support […]

May 8, 2014May 11, 2014 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Imperas Releases ARM Cortex A53 & A57 Open Source Models for OVPsim

Since the end of 2012, it has been possible to use ARM 64-bit Fast models to run code compiled for the new ARMv8 architecture by emulating a 64-bit ARM processor inside an Intel / AMD processor. ARM fast models are not the only “free” option anymore, as Imperas has released OVPsim 20140430 with open source models for ARM Cortex A53 and Cortex A57 cores. OVPsim is a virtual platform that’s available free of charge for personal usage. The simulator itself (OVPsim) is closed source, but processor, peripheral and platform models are released under the Apache License version 2.0. OVP models of the ARM Cortex-A53 and Cortex-A57 are fully instruction accurate models, and you can use them for personal with an additional free license key, but if you want to make use of advanced features such as TrustZone and hardware virtualization you’ll need to purchase a commercial version (Imperas Developer or […]

May 6, 2014 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

ARM Based COM Express Modules by MEN Mikro Electronik and Pactron

A few days ago, in a post listing different system-on-module (SoM) standards, I mentioned COM Express standard was targeting SoMs based on x86 processors, and SMARC was the equivalent for ARM. I still understand it’s the case as COM Express standard defines mechanical dimensions that are usually larger than SoM standard for low power processors, some buses found in ARM and x86 are different (e.g. AFAIK LPC and PCI are not found in ARM SoC), and the standard supports high power signals which are not needed in ARM or MIPS processors. Having said that, I’ve been pointed out to two ARM based COM Express modules, which could make sense if you want to use an ARM based module using existing COM Express compatible baseboards. The COM Express modules below feature Freescale i.MX6 and Marvell Armada XP SoCs, and have been designed respectively by MEN Mikro Electronik and Pactron. MEN Mikro […]

May 6, 2014 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

AMD Announces ARM and x86 pin-to-pin Compatible APUs and SoCs for 2015, ARM K12 Core for 2016 and Beyond

AMD has designed x86 processor since its inception, and recently they’ve announced ARM Cortex A57 “Seatlle” SoCs targeting servers would be available later this year. They’ve now decided to merge their product line-up even further with Project Skybridge that aims to provide pin-to-pin compatible ARM and x86 SoCs and APUs by 2015, manufactured using a 20nm process. That means AMD’s customers should be able to leverage AMD’s “ambidextrous computing” solutions to design one and only board for x86 and ARM processors for server, embedded, semi-custom and ultra-low power applications. Processors of the “Project Skybridge” family will also be the first ARM based AMD processors to include a GPU (Graphics Core Next GPU), contrary to Seatlle SoCs, which are destined to be used for the server market, and do not come with a GPU. ARM processor will be based on low power ARM Cortex A57 cores and x86 processors will make […]