Elkhart Lake processors integrate the Intel Programmable Services Engine (Intel PSE) offload engine for IoT workloads powered by an Arm Cortex-M7 microcontroller that handles real-time IO control using GPIO, I2C, and/or UART interfaces, and supports functions such as remote, out-of-band device management, network proxy, embedded controller, and sensor hub. Until now the firmware was only provided as a closed-source binary, and Coreboot developers published an open letter to open the source code for the PSE firmware last December, and it’s been successful with Intel releasing the Intel PSE SDK based on Zephyr OS. The SDK combines open-source components (code samples, services, etc…) released under a permissive Apache 2.0 license (“License A”), and closed-source libraries and tools released under an Intel license (“License B”) allowing the redistribution and use in binary form, without modification. You’ll find everything on Github including documentation explaining how to get started with the Zephyr SDK, the […]
QEMU 7.0 released with support for RISC-V KVM, Intel AMX, and more
QEMU (Quick EMUlator) is an open-source emulator used to run OS or programs on various architectures such as Arm, RISC-V, and many others when you don’t own specific hardware, or for quick testing. The developers have released QEMU 7.0 a few days ago with over 2500 commits from 225 developers. New features include support for RISC-V KVM and vector extensions, Intel AMX (Advanced Matrix Extension), improved flexibility for fleecing backups, various new features for Arm, and many more. QEMU 7.0 highlights listed by the developers: ACPI: support for logging guest events via ACPI ERST interface virtiofs: improved security label support block: improved flexibility for fleecing backups, including support for non-qcow2 images ARM: ‘virt’ board support for virtio-mem-pci, specifying guest CPU topology, and enabling PAuth when using KVM/hvf ARM: ‘xlnx-versal-virt’ board support for PMC SLCR and emulating the OSPI flash memory controller ARM: ‘xlnx-zynqmp’ now models the CRF and APU control […]
Arm SystemReady SR-certified Ampere Altra Developer Platform launched for $3,999
ADLINK has just announced the availability of the Arm SystemReady SR-certified Ampere Altra Developer Platform equipped with the company’s COM-HPC Ampere Altra module with 32 to 80 64-bit Arm Neoverse N1 cores, 32GB to 128GB RAM. An adaptation to the earlier AVA Developer Platform expected to sell for $5,450, the Ampere Altra Developer Platform got a price cut to $3,999 at launch for a system with a 32-core processor, and 32GB DDR4. The system targets software developers wanting to build cloud-to-edge applications using standardized Arm hardware. Ampere Altra Developer Platform specifications: SoM – COM-HPC Ampere Altra module with Ampere Altra 32 to 80-core 64-bit Arm Neoverse N1 processor up to 1.7/2.2/2.6 GHz (32/64/80 cores, TPD: 60W to 175W), 32 GB to 128GB DDR4 ECC memory Storage – 128 GB NVMe M.2 SSD Mainboard – COM-HPC Server Base carrier board Video – VGA port Audio – 3.5mm audio jack Networking 1x […]
Lakka 4.0 game emulator released with LibreELEC 10.0.2 and RetroArch 1.10.1
Lakka 4.0 is the latest release of the game emulator based on LibreELEC 10.0.2 and RetroArch 1.10.1 frontend GUI for LibRetro game emulators cores. While Lakka was initially designed for Raspberry Pi boards in a way similar to RetroPie, it also works just fine on many other Arm platforms and PCs. Main changes to Lakka 4.0 compared to version 3.7: Build system based on LibreELEC 10.0.2 RetroArch updated to 1.10.1 Cores updated to their most recent versions superbroswar: added new libretro core sameduck: added new libretro core Mesa updated to 22.0.0 Mainline kernel updated to 5.10.103 (PC, Amlogic, Allwinner, NXP) Raspberry kernel updated to 5.10.95 Most arm devices switched to aarch64 Rockchip RK3288, RK3328 and RK3399 switched to mainline kernel 5.10.76 Added support for additional Allwinner and Amlogic devices (not tested on our side, as we do not own many of these devices) Nintendo Switch: complete rewrite of the port […]
Linux 5.17 release – Main changes, Arm, RISC-V, and MIPS architectures
Linus Torvalds has just released Linux 5.17: So we had an extra week of at the end of this release cycle, and I’m happy to report that it was very calm indeed. We could probably have skipped it with not a lot of downside, but we did get a few last-minute reverts and fixes in and avoid some brown-paper bugs that would otherwise have been stable fodder, so it’s all good. And that calm last week can very much be seen from the appended shortlog – there really aren’t a lot of commits in here, and it’s all pretty small. Most of it is in drivers (net, usb, drm), with some core networking, and some tooling updates too. It really is small enough that you can just scroll through the details below, and the one-liner summaries will give a good flavor of what happened last week. Of course, this means […]
Picovoice on-device speech-to-text engines slash the requirements and cost of transcription
Picovoice Leopard and Cheetah offline, on-device speech-to-text engines are said to achieve cloud-level accuracy, rely on tiny Speech-to-Text models, and slash the cost of automatic transcription by up to 10 times. Leopard is an on-device speech-to-text engine, while Cheetah is an on-device streaming speech-to-text engine, and both are cross-platform with support for Linux x86_64, macOS (x86_64, arm64), Windows x86_64, Android, iOS, Raspberry Pi 3/4, and NVIDIA Jetson Nano. Looking at the cost is always tricky since companies have different pricing structures, and the table above basically shows the best scenario, where Picovoice is 6 to 20 times more cost-effective than solutions from Microsoft Azure or Google STT. Picovoice Leopard/Cheetah is free for the first 100 hours, and customers can pay a monthly $999 fee for up to 10,000 hours hence the $0.1 per hour cost with PicoVoice. If you were to use only 1000 hours out of your plan that […]
UCIe (Universal Chiplet Interconnect Express) open standard for Chiplets with heterogeneous chips
We first heard about Chiplet, chips that gather IP or chips from different vendors into a single chip, in 2020 with the now-defunct zGlue’s Open Chiplet Initiative, but the term recently came back to the forefront last month with Intel’s investment into the “Open Chiplet Platform” that aims to offer a modular approach to chip design through chiplets with each block/chiplet customized for a particular function. It turns out there’s now an official standard called the Universal Chiplet Interconnect Express (UCIe) whose specification defines the interconnect between chiplets within a package, and not only backed by Intel, but also AMD, Arm, ASE, Google Cloud, Meta, Microsoft, Qualcomm, Samsung, and TSMC. UCIe defines the Physical Layer (Die-to-Die I/O) and protocols to be used for the chiplet interfaces, currently PCIe and CXL (Compute Express Link), but more protocols will be added to the specification in the future. The goal is to provide […]
Low-power satellite IoT SoC works with Totum’s Low Earth Orbit (LEO) network
Orca Systems ORC3990 is a low-power satellite Internet of Things (IoT) SoC that works with Totum’s Low Earth Orbit (LEO) network of satellites and targets outdoor and indoor tracking and monitoring applications. It’s not the first time we read about satellites being used for LPWAN networks, as Sigfox launched LEO satellites a few years ago to provide worldwide coverage even in remote locations like the Sahara desert, the two poles, and oceans. But I had never heard of Totum or Orca Systems before, so let’s have a closer look. Orca Systems ORC3990 ORC3990 specifications: Unnamed Arm cores Integrated RF Transceiver Low Power Sensor-to-Satellite (LP-S2S) connectivity in the 2.4 GHz ISM band Totum DMSS modem for improved doppler performance Link budget enables indoor signal coverage Support location fixes with 20m accuracy Low power – 10+ year battery life Package – 7x7mm QFN chip Temperature Range – -40 – +85°C Process – […]