arm News - CNX Software - Embedded Systems News

November 18, 2024November 18, 2024 by Tomisin Olujinmi - No Comments

Qualcomm QCC730M dual-band WiFi 4 and QCC74xM WiFi 6, BLE 5.3, and 802.15.4 modules target low-power and IoT edge devices

Qualcomm has added two new IoT modules to its wireless connectivity product series: the Qualcomm QCC730M ‘micro-power’ WiFi 4 module and the QCC74xM tri-radio module, with both modules designed for smart homes, smart appliances, medical devices, and industrial applications. The Qualcomm QCC730M is a dual-band, micro-power Wi-Fi 4 module with a 60MHz Arm Cortex-M4F MCU, 640kB SRAM, 1.5MB RRAM, hardware crypto accelerator, and secure boot, debug, and storage. Its low-power design is ideal for portable, battery-powered IoT devices like IP cameras, sensors, and smart locks. Based on the Qualcomm QCC730 module, it features a 36-pin LGA package with a PCB antenna or RF connector and supports up to 4MB of optional NOR flash. The Qualcomm QCC74xM is Qualcomm’s “first programmable connectivity module,” integrating a 32-bit RISC-V module, optional stacked memory (PSRAM and NOR flash), and a tri-radio chipset for WiFi 6, Bluetooth 5.3, and IEEE 802.15.4 (Thread and Zigbee). Its […]

November 14, 2024November 13, 2024 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

AMD Versal Premium Gen2 SoC FPGA family features Arm Cortex-A72/R5F cores, high-end FPGA fabric, PCIe Gen6, CXL 3.1 interfaces

AMD Versal Premium Series Gen 2 SoC FPGA combines dual-core Cortex-A72 and dual-core Cortex-R5F processors with high-end FPGA fabric with up to 3.2 million logic cells and CXL 3.1 (Compute Express Link), PCIe Gen6, and DDR5/LPDDR5X high-bandwidth interfaces for data center, communication equipment, test & measurement, and aerospace & defense data-intensive applications. AMD Versal Premium Gen2 specifications: CPU cores Dual-core Arm Cortex-A72 application core, 48 KB/32 KB L1 Cache w/ parity & ECC; 1 MB L2 Cache w/ ECC Dual-core Arm Cortex R5F, 32 KB/32 KB L1 Cache, and 256 KB TCM w/ECC Memory – 256MB on-chip with ECC FPGA fabric System Logic Cells – Up to 3,273,480 LUTs – Up to 1,496,448 DSP Engines – Up to 7,616 Interfaces connected to CPU cores 2x Ethernet 2x UART, 2x SPI, 2x I2C 2x CAN-FD 1x USB 2.0 FPGA memory, interfaces, I/Os, and transceivers Up to 327 Mbit memory @ 273 […]

November 13, 2024November 15, 2024 by Jean-Luc Aufranc (CNXSoft) - 10 Comments

GenBook RK3588 modular Linux laptop features an octa-core Arm CPU module with 32GB RAM (Crowdfunding)

GenBook RK3588 is a modular Linux (and Android) laptop powered by a Rockchip RK3588 Arm system-on-module (SoM), and easily serviceable by the user who can add M.2 MVMe SSD storage, switch wireless module, and eventually update to a more powerful SoM, or even change the display. It looks very similar to the Cool Pi Arm Linux laptop, and it’s indeed made by the same company, but a representative told CNX Software that the GenBook RK3588 was an upgrade of the Cool Pi without further details. So let’s have a closer look. GenBook RK3588 laptop specifications: System-on-Module – GenM5 (same as Cool Pi CM5 except for the move from LPDDR4/4X to LPDDR5) SoC – Rockchip RK3588 octa-core processor with 4x CortexA76 cores, 4x CortexA55 cores Arm Mali-G610 MP4 GPU Video decoder – 8Kp60 H.265, VP9, AVS2, 8Kp30 H.264 AVC/MVC, 4Kp60 AV1, 1080p60 MPEG-2/-1, VC-1, VP8 Video encoder – 8Kp30 H.265/H.264 video […]

November 1, 2024November 2, 2024 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

MicroPython v1.24 release adds support for RP2350 and ESP32-C6 microcontrollers, various RISC-V improvements

Micropython v1.24 with ESP32-C6 and RP2350 support

MicroPython has become one of the most popular ways of programming microcontrollers, and the just-released MicroPython v1.24 adds support for the widely-used Raspberry Pi RP2350 and Espresif ESP32-C6 microcontrollers and a range of other changes. Those include improved RISC-V support with native code generation, an updated Zephyr v3.7.0 RTOS with threading support, unified TinyUSB bindings across ports, a portable UART IRQ API, and enhanced mpremote recursive copy. Damien George goes into more detail about the RISC-V improvements: … include an RV32IMC native code emitter, native NLR and GC register scanning implementations for 32- and 64-bit RISC-V, support for placing RV32IMC native code in .mpy files and also freezing it, and RISC-V semihosting support. Testing for RISC-V is done with the qemu and unix ports, and the support is utilised in the esp32 and rp2 ports. The Raspberry Pi RP2350 comes with both Arm Cortex-M33 and RISC-V cores, and the good […]

October 4, 2024October 5, 2024 by Jean-Luc Aufranc (CNXSoft) - 14 Comments

Upcoming Rockchip RK3688 Armv9.3 AIoT processor to feature a 16 TOPS NPU, UFS 4.0 interface

Rockchip has unveiled the RK3688 AIoT SoC with Armv9.3 Cortex-A7xx cores delivering up to 250K DMIPS (RK3588 delivers 93K DMIPS), a 1 TFLOPS GPU, and a 16 TOPS NPU. The new processor succeeds the Rockchip RK3588 octa-core Cortex-A76/A55 first announced in 2019, and also features a 128-bit LPDDR4/4x/5 memory interface, and a UFS 4.0 storage interface. That’s about all we know about the RK3688 right now, but we can also deduct it’s probably based on a new, yet-to-be-announced Arm Cortex-A7xx core, possibly named Cortex-A730 or Cortex-A735, because no Arm cores have been announced with the Armv9.3 architectures. The Arm Cortex-A725 CPU core unveiled last May still relies on Armv9.2, and I’d expect new Arm cores to be introduced within the next few months unless Rockchip made a mistake in the presentation slide above. Two other platforms were also announced at the same time starting with a new entry-level/mid-range RK35XX octa-core […]

October 1, 2024September 30, 2024 by Debashis Das - 4 Comments

Altera’s 7nm Agilex 3 SoC FPGA features Cortex-A55 cores, AI Tensor Block, DSP, 10 GbE, and more.

Altera, an independent subsidiary of Intel, has launched the Altera Agilex 3 SoC FPGA lineup built on Intel’s 7nm technology. According to Altera, these FPGAs prioritize cost and power efficiency while maintaining essential performance. Key features include an integrated dual-core Arm Cortex A55 processor, AI capabilities within the FPGA fabric (tensor blocks and AI-optimized DSP sections), enhanced security, 25K–135K logic elements, 12.5 Gbps transceivers, LPDDR4 support, and a 38% lower power consumption versus competing FPGAs. Built on the Hyperflex architecture, it offers nearly double the performance compared to previous-generation Cyclone V FPGAs. These features make this device useful for manufacturing, surveillance, medical, test and measurement, and edge computing applications. Altera’s Agilex 3 AI SoC FPGA specifications Device Variants B-Series – No definite information is available C-Series – A3C025, A3C050, A3C065, A3C100, A3C135 SoC FPGAs Hard Processing System (HPS) – Dual-core 64-bit Arm Cortex-A55 up to 800 MHz that supports secure […]

September 27, 2024September 26, 2024 by Debashis Das - No Comments

ADLINK AVA-1000 is a rugged EN50155-compliant T2G gateway for railway and industrial applications

The ADLINK AVA-1000 T2G gateway is a rugged, EN50155-compliant T2G (Train-to-Ground) gateway designed for railway and industrial environments. Powered by a choice of NXP i.MX8M Plus Quad Cortex-A53 processor or an Intel Processor N50 Alder Lake-N processor. The i.MX8M Plus model is equipped with up to 8GB LPDDR4 and a 64GB eMMC flash whereas the Alder Lake variant features up to 4GB LPDDR5 memory and a 32GB eMMC flash. In terms of connectivity, the gateway features three M12 GbE ports and supports a wide range of options including 5G, WiFi 6, and GNSS. The AVA-1000 T2G gateway’s fanless design, wide operating temperature range, and 24-110V DC input ensure reliable operation in industrial environments. Additionally, its compliance with EN50155 and other industrial standards makes it ideal for various industrial applications. AVA-1000 T2G gateway specifications System Processor (multiple options) NXP i.MX8M Plus quad-core Cortex-A53 processor @ up to 1.8 GHz with Cortex-M7 […]

September 16, 2024 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Linux 6.11 Release – Notable changes, Arm, RISC-V and MIPS architectures

Linux 6.11 is out with Linus Torvalds’ announcement on the Linux kernel mailing list (LKML): I’m once again on the road and not in my normal timezone, but it’s Sunday afternoon here in Vienna, and 6.11 is out. The last week was actually pretty quiet and calm, which is nice to see. The shortlog is below for anybody who wants to look at the details, but it really isn’t very many patches, and the patches are all pretty small. Nothing in particular stands out – the biggest patch in here is for Hyper-V Confidential Computing documentation. Anyway, with this, the merge window will obviously open tomorrow, and I already have 40+ pull requests pending. That said, exactly _because_ I’m on the road, it will probably be a fairly slow start to the merge window, since not only am I on my laptop, there’s OSS Europe starting tomorrow and then the […]