risc-v News - Page 7 of 51 - CNX Software

April 2, 2024 by Jean-Luc Aufranc (CNXSoft) - 11 Comments

Avaota A1 open-source hardware SBC is powered by Allwinner T527 octa-core Cortex-A55 SoC

Avaota A1 open-source hardware Allwinner T527 SBC

We’ve recently covered MYiR Tech MYD-LT527 industrial development board based on Allwinner T527 octa-core Cortex-A55 AI SoC and noted Orange Pi is working on one that should even get mainline Linux support. The Avaoto A1 offers another Allwinner T527 hardware option with an SBC design that’s fully open-source. The board is equipped with up to 4GB RAM, 128GB eMMC flash, HDMI and DisplayPort video outputs, two gigabit Ethernet ports, a WiFi 6 and Bluetooth 5.4 module, a few USB ports, a 3.5mm audio jack and the usual 40-pin GPIO header for expansion. Avaota A1 specifications: SoC – Allwinner T527 (or Allwinner A527 with Avaota A1C board, not sure what the differences are between the two) CPU Octa-core Arm Cortex-A55 processor with four cores @ 1.80 GHz and four cores @ 1.42GHz XuanTie E906 RISC-V core up to 200 MHz GPU – Arm Mali-G57 MC1 GPU with support for OpenGL ES […]

March 29, 2024March 31, 2024 by Jean-Luc Aufranc (CNXSoft) - 15 Comments

Orange Pi Developer Conference 2024, upcoming Orange Pi SBCs and products

Orange Pi held a Developer Conference on March 24, 2024, in Shenzhen, China, and while I could not make it, the company provided photos of the event where people discussed upcoming boards and products, as well as software support for the Orange Pi SBCs. So I’ll go through some of the photos to check out what was discussed and what’s coming. While Orange Pi is mostly known for its development boards the company has also been working on consumer products including the Orange Health Watch D Pro and the OrangePi Neo handheld console. The Orange Pi Watch D Pro is said to implement non-invasive blood glucose monitoring, blood pressure monitoring, one-click “micro-physical examination” and other functions to to help users monitor their health monitoring. The Watch D Pro uses a technique that emits a green light to measure glucose levels in the blood, and we’re told it’s accurate enough to […]

March 28, 2024March 27, 2024 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

LoLRa project – Transmitting LoRa packets without radio using CH32V003, ESP8266, or ESP32-S2 MCU

The LoLRa project is a firmware-only LoRa transmission open-source project that works without a Semtech radio and instead relies on an I2S or SPI interface (so not exactly bit-banging) to transmit data with microcontrollers such as WCH CH32V003, or Espressif Systems ESP8266 and ESP32-S2 microcontrollers. LoRa is a proprietary protocol by Semtech, but people have been trying to reverse-engineer the LoRa PHY for years, and this culminated with a LoRa GNU Radio SDR implementation last year. But CNLohr found out you don’t even need a radio to send LoRa packets and you can instead use SPI or I2S interfaces from general-purpose microcontrollers to send packets that can be decoded by commercial off-the-shelf LoRa gateways and other chips. The current implementation is designed for the ITU Region 2 (aka The Americas) targeting the 902-928MHz frequency band, but the code could be changed for Region 1 (EU, Russia, Africa) to target 863-870MHz […]

March 27, 2024March 27, 2024 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

R9A02G021 is the first microcontroller with Renesas 32-bit RISC-V CPU core design

Renesas R9A02G021 is the first MCU group to use the company’s in-house designed 32-bit RISC-V CPU core with 3.27 CoreMark/MHz, RV32I base plus M/A/C/B extensions, and features such as a stack monitor register, a dynamic branch prediction unit, and a JTAG debug interface. Renesas has been making RISC-V chips at least since 2022 with the likes of RZ/Five 64-bit microprocessor and R9A06G150 32-bit voice control ASSP. All those were based on Andes RISC-V cores, but since the company has now designed its own 32-bit core, future Renesas 32-bit RISC-V microcontrollers are all likely to feature the in-house core, starting with the R9A02G021 general-purpose MCU group. Renesas R9A02G021 key features and specifications: RISC-V Core Renesas RISC-V instruction-set architecture (RV32I + MACB + Ziscr, Control and Status Register (CSR) instructions + RISC-V Zifencei Instruction-Fetch Fence) Maximum operating frequency – 48 MHz Debug and Trace – RISC-V External Debug Support cJTAG Debug Port […]

March 25, 2024June 26, 2024 by Jean-Luc Aufranc (CNXSoft) - 16 Comments

Duo S RISC-V/Arm SBC features Sophgo SG2000 SoC, Ethernet, WiFi 6, and Bluetooth 5 connectivity

Duo S SBC Sophgo SG2000 Ethernet WiFi 6 Bluetooth

Shenzhen MilkV Technology’s Duo S is a tiny SBC based on the 1 GHz Sophgo SG2000 Arm Cortex-A53 and RISC-V SoC with 512MB DDR3 (SiP), Fast Ethernet, WiFi 6, and Bluetooth 5 connectivity, and a switch to select Arm or RISC-V architecture before powering the board. We already had covered SG2002 Arm/RISC-V boards with 256MB RAM, namely the LicheeRV Nano and Duo 256M, but for people needing more memory, the Duo S provides another option that also features two 2-lane MIPI CSI connectors, a USB 2.0 host port, and two 26-pin headers for expansion. Its form factor reminds me of FriendlyELEC’s NanoPi NEO and family powered by Allwinner processors that were introduced a few years ago. Duo S specifications: SoC – SOPHGO SG2000 Main core – 1 GHz 64-bit RISC-V C906 or Arm Cortex-A53 core (selectable) Minor core – 700 MHz 64-bit RISC-V C906 core Low-power core – 25 to […]

March 22, 2024August 13, 2024 by Jean-Luc Aufranc (CNXSoft) - No Comments

Efinix Titanium Ti375 FPGA offers quad-core hardened RISC-V block, PCIe Gen 4, 10GbE

Efinix Titanium Ti375 SoC combines high-density, low-power Quantum compute fabric with a quad-core hardened 32-bit RISC-V block and features a LPDDR4 DRAM controller, a MIPI D-PHY for displays or cameras, and 16 Gbps transceivers enabling PCIe Gen 4 and 10GbE interfaces. The Titanium Ti375 also comes with 370K logic elements, 1.344 DSP blocks, 2,688 10-Kbit SRAM blocks, and 27,53 Mbits embedded memory, as well as DSP blocks optimized for computing and AI workloads, and XLR (eXchangeable Logic and Routing) cells for logic and routing. Efinix Titanium Ti375 specifications: FPGA compute fabric 370,137 logic elements (LEs) 362,880 eXchangeable Logic and Routing (XLR) cells 27,53 Mbits embedded memory 2,688 10-Kbit SRAM blocks 1,344 embedded DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting Memory – 10-kbit high-speed, embedded SRAM, conﬁgurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM FPGA interface blocks 32-bit quad-core hardened RISC-V block […]

March 19, 2024March 18, 2024 by Tomisin Olujinmi - 12 Comments

TinyVision is a compact Allwinner V851S/V851S3-powered Linux board for vision-based applications

Unrelated to tinyVision.ai, the TinyVision development board is a computer vision board from Chinese developer YuzukiTsuru powered by either the Allwinner V851S or the V851S3 and is billed as an “ultimate all-in-one solution for Linux motherboards, IPCs, servers, routers, and more.” It packs features such as a Cortex-A7 core running at 1200MHz, a 2-channel MIPI CSI input, and an independent image signal processor (ISP) capable of a maximum resolution of 2560 x 1440 in a compact form factor. TinyVision specifications: Processor – Allwinner V851SE / V851s3 with Cortex-A7 core @ 1200MHz and RISC-V E907GC core @ 600MHz NPU: 0.5TOPS (tera operations per second) @ INT8 precision Memory – 64MB DDR2 (V851se), 128MB DDR3L (V851s3) Storage – MicroSD card slot (supports UHS-SDR104), onboard SD NAND via SPI Display – 2-lane MIPI DSI (1280 x 720 @ 60fps), RGB LCD (320 x 240 @ 60fps) Video Input ISP with a maximum resolution […]

March 11, 2024 by Jean-Luc Aufranc (CNXSoft) - No Comments

Linux 6.8 release – Notable changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just announced the release of Linux 6.8 on the Linux kernel mailing list: So it took a bit longer for the commit counts to come down this release than I tend to prefer, but a lot of that seemed to be about various selftest updates (networking in particular) rather than any actual real sign of problems. And the last two weeks have been pretty quiet, so I feel there’s no real reason to delay 6.8. We always have some straggling work, and we’ll end up having some of it pushed to stable rather than hold up the new code. Nothing worrisome enough to keep the regular release schedule from happening. As usual, the shortlog below is just for the last week since rc7, the overall changes in 6.8 are obviously much much bigger. This is not the historically big release that 6.7 was – we seem to […]