risc-v

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on More Details about Alibaba XT910 64-bit RISC-V Core

More Details about Alibaba XT910 64-bit RISC-V Core

Xuantie XT902, XT9xx, XT910

Alibaba unveiled XuanTie 910 16-core RISC-V Processor last year with few details except it targetted high-performance 5G, AI, and autonomous driving applications. The company has now provided more details about Alibaba XuanTie 910 (aka XT910) processor during the virtual Hot Chips 2020 conference, and he notably compared the RV64GCV core found in the processor to Arm Cortex-A73 core. Alibaba XT910 main features and specifications: CPU – Up to 16x 64-bit RISC-V (RV64GCV) cores with RISC-V Vector extension and custom Turbo extension in four clusters of four cores; 12-stage out of order; Coremark: 7.1 per MHz Cache – 32KB or 64KB I/D cache per core, up to 8MB L2 cache per cluster FP16-FP64 floating-point unit Vector Computing Unit (aka Vector Engine) for AI acceleration Memory Management – Sv39 MMU + 8/16 PMP Interrupt Controller – Clint + PLIC Process – Final: 12nm FinFET; engineering samples: TSMC 28nm HPC Alibaba RISC-V Turbo […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 13 Comments on Sipeed Maix Amigo is a Portable 64-bit RISC-V AI Development Kit with Display and Cameras

Sipeed Maix Amigo is a Portable 64-bit RISC-V AI Development Kit with Display and Cameras

Sipeed Maix Amigo

Earlier this year, Seeed Studio introduced Wio Terminal a portable Arduino devkit with an LCD display, and expansion connectors and headers. The company is now selling a similar looking devkit but for different applications with Sipeed Maix Amigo portable 64-bit RISC-V development kit powered by Kendryte K210 RISC-V AI processor and equipped with an LCD display, two cameras, a few buttons, and several I/O headers and Grove connectors. Sipeed Maix Amigo specifications: SoC – Kendryte K210 Dual-core 64-bit RISC-V (RV64GC) processor with FPU @ 400 MHz (overclockable to 500MHz), 8MB SRAM, built-in AI accelerators for video and audio Storage – 16MB Flash, MicroSD card slot up Display – 3.5-inch TFT capacitive touch screen display with 480×320 resolution Camera VGA front-facing camera up to 30 fps (GC0328 sensor) VGA rear camera up to 60 fps (OV7740 sensor) Audio – Build-in microphone, optional 6-mic array USB – 1x USB Type-C port for […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on Linux 5.8 Release – Main Changes, Arm, MIPS, and RISC-V Architectures

Linux 5.8 Release – Main Changes, Arm, MIPS, and RISC-V Architectures

Linux 5.8 Release

Linus Torvalds has just released Linux 5.8: So I considered making an rc8 all the way to the last minute, but decided it’s not just worth waiting another week when there aren’t  any big looming worries around. Because despite the merge window having been very large, there really hasn’t been anything scary going on in the release candidates. Yeah, we had some annoying noise with header file dependencies this week, but that’s not a new annoyance, and it’s also not the kind of subtle bug that keeps me up at night worrying about it. It did reinforce how nice it would be if we had some kind of tooling support to break nasty header file dependencies automatically, but if wishes were horses.. Maybe some day we’ll have some kind of SAT-solver for symbol dependencies that can handle all our different architectures and configurations, but right now it’s just a manual […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on SiFive RISC-V Processors Get Performance & Efficiency Improvements, Smaller Footprint with 20G1 Release

SiFive RISC-V Processors Get Performance & Efficiency Improvements, Smaller Footprint with 20G1 Release

SiFive Core IP 20G1 Release

SiFive RISC-V cores portfolio ranges from low power 32-bit IoT processors to more powerful, Linux-capable 64-bi RISC-V cores like the latest SiFive U84/U87 cores rivaling with Arm Cortex-A7x cores. SiFive Core IP 20G1 release further enhances the company’s existing RISC-V cores with performance improvements, higher efficiency, and a smaller footprint. Specifically, SiFive claims the SiFive U7-Series has increased load bandwidth up to 2.8x for memory-intensive workloads such as AI inference processing, and all of the company’s RISC-V cores can now run at lower power, with the SiFive U74 standard core running at up to 25% lower power while running Dhrystone benchmark. The SiFive E-Series processors which feature real-time capability are now available with the RISC-V Embedded extension (RV32E) which reduces the footprint compared to RV32I ISA with for instance up to 11% smaller area for the SiFive E3-Series. RV32E and RV32I have the same instructions set, but RV32E comes with […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on WCH CH569 RISC-V SoC Offers USB 3.0, Gigabit Ethernet, High-Speed SERDES & HSPI Interfaces

WCH CH569 RISC-V SoC Offers USB 3.0, Gigabit Ethernet, High-Speed SERDES & HSPI Interfaces

CH569 RISC-V SoC

RISC-V open architecture has made its way into low-cost low power general purpose MCUs such as Gigadevices GD32V or WCH CH32V103, Western Digital hard drives, some AI processors notably Kendryte K210, and even Linux capable boards including Microsemi’s PolarFire SoC Icicle kit. But more applications featuring RISC-V architecture are coming with, for instance, WCH CH569 RISC-V processor featuring USB 3.0, Gigabit Ethernet, DVP camera, and 1.25 SERDES block all managed by a RISC-V core clocked at 120 MHz. CH569 (and CH565) processor key features and specifications: CPU – RISC-V (RISC-V3A) core @ 120MHz with hardware multiplication and division, programmable interrupt controller, low-power two-stage pipeline Memory – 16KB 32-bit SRAM, 32/64/96KB configurable 128-bit SRAM Storage Internal – 448KB code flash, 32KB data flash External – SD/eMMC controller with single-wire, 4-wire, 8-wire data communication mode. Complies with eMMC card 4.4 and 4.5.1 specifications, and compatible with 5.0 specifications Networking – Gigabit Ethernet […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on PolarFire SoC Icicle 64-bit RISC-V and FPGA Development Board Runs Linux or FreeBSD (Crowdfunding)

PolarFire SoC Icicle 64-bit RISC-V and FPGA Development Board Runs Linux or FreeBSD (Crowdfunding)

PolarFire SoC Icicle Kit

We got some more details about PolarFire RISC-V FPGA SoC late last year, and we were promised a Linux capable 64-bit RISC-V & FPGA development board with PolarFire SoC Icicle kit in Q3 of 2020. We are already in July 2020. So where is the board? Oh, look! It’s right here on Crowd Supply where it is offered for $499, and shipping is expected to start in mid-September. PolarFire SoC Icicle specifications: SoC FPGA – PolarFire SoC MPFS250T-FCVG484EES penta–core RISC-V CPU subsystem (1xRV64IMAC, 4xRV64GC) with 254K LE non-volatile fabric, 784 18 × 18 math blocks, secure boot, 4x 12.7 Gbps SERDES, FCVG484 package (19 × 19 mm, 0.8 mm pitch) System Memory – 2GB LPDDR4 x32 Storage – 1 GBit QSPI Flash, 8GB eMMC Flash or SD card slot (multiplexed) Video Output – HDMI 2.0 (removed from final board) Connectivity – 2x Gigabit Ethernet, Wi-Fi, and Bluetooth USB – 1x […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Upcoming SAVVY-V Open Source RISC-V Cluster Board Supports 10GbE via Microsemi PolarFire 64-bit RISC-V SoC

Upcoming SAVVY-V Open Source RISC-V Cluster Board Supports 10GbE via Microsemi PolarFire 64-bit RISC-V SoC

SAVVY-V Open Source-PolarFire RISC-V SOC FPGA Board

RISC-V based PolarFire SoC FPGA by Microsemi may be coming up in the third quarter of this year, but Ali Uzel has been sharing a few details about SAVVY-V advanced open-source RISC-V cluster board made by FOSOH-V (Flexible Open SOurce Hardware for RISC-V) community of developers. It’s powered by Microsemi Polarfire RISC-V SoC MPFS250T with four 64-bit RISC-V cores, a smaller RV64IMAC monitor core, and FPGA fabric that allows 10GbE via SFP+ cages, and exposes six USB Type-C ports. The solution is called a cluster board since up to six SAVVY-V boards can be stacked via a PC/104+ connector and interfaced via the USB-C ports. SAVVY-V cluster board preliminary features and specifications: SoC – Microsemi Polarfire RISC-V SoC MPFS250T with a quad-core 64-bit RV64IMAFDC (RV64GC) processor @ up to 667 MHz, a RV64IMAC monitor core, and FPGA fabric with 250K logic elements; 3.0 CoreMarks/MHz, 2.0 DMIPs/MHz; Also compatible with MPFS160T, […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on zGlue Launches the Open Chiplet Initiative in Collaboration with Google and Antmicro

zGlue Launches the Open Chiplet Initiative in Collaboration with Google and Antmicro

Open Chiplet Initiative

We first covered zGlue’s ZiP (zGlue Integration Platform) in 2018 as the company introduced its multi-chip module similar to SiP (system-in-package) via a crowdfunding campaign. Just like SiP, the technology packages several components into a single package, but costs have been brought down to enable low-volume production of custom chips for a reasonable price. Since then the company announced new ZiP multi-chip modules such as nRF52832 based Omnichip and the FPGA, Arm or/and RISC-V based GEM ASIC by Antmicro. The company recently announced the Open Chiplet Initiative, a collection of open-source designs, tools and file formats, launched in collaboration with Google and  Antmicro. There are four main types of tools within the Open Chiplet Initiative: Open Chiplet Interfaces – Currently only ZEF (zGlue Chiplet Info Exchange Format) is provided. It defined the part numbers, pins, and mechanical dimensions of various parts. The ZEF specification can be found on Github. Design […]

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