risc-v News - Page 36 of 51 - CNX Software

December 20, 2020January 11, 2022 by Jean-Luc Aufranc (CNXSoft) - 34 Comments

ESP32-C3 WiFi & BLE RISC-V processor to launch at ESP8266 price

[Update December 2020: While we first reported ESP32-C3 would be pin-to-pin compatible to ESP8266 based on the tweet mentioned in the post, the datasheets show both are clearly not pin-to-pin compatible, and instead it looks like the goal is to provide pin-to-pin compatible modules] When we reported about ESP32-S2-MINI modules last September, we also noted Espressif teased us with ESP32-S3 and ESP32-C3 with close to no details. ESP32-S3 is expected to be a multi-core WiFI & Bluetooth processor with AI instructions/accelerator, but there were no details about ESP32-C3 at all, and we only found out it would be a RISC-V processor several weeks ago. But Twitter user Johnny Wu posted a screenshot in Chinese and its translation claiming ESP32-C3 was finally released by Espressif Systems. [Update: The datasheet has been released. See comments.] ESP32-C3 WiSoC is pin to pin compatible with ESP8266, works with ESP32 development framework (e.g. ESP-IDF), supports […]

December 17, 2020 by Jean-Luc Aufranc (CNXSoft) - No Comments

Cmsemicon ANT32RV56xx is a RISC-V microcontroller for wireless charging

We’ve seen RISC-V architecture used in general-purpose microcontrollers, AIoT processors, as well as WiFi and Bluetooth IoT SoC’s such as ESP32-C3 and BL602. Allwinner is also prepping a RISC-V application processor, and we’ve covered plenty of other developments in our RISC-V 2020 highlights post. But we’ve now been made aware of another application-specific RISC-V microcontroller from a Chinese fabless vendor I had never heard of. Meet Cmsemicon ANT32RV56xx RISC-V microcontroller for wireless charging applications. Cmsemicon ANT32RV56xx “tentative” key features and specifications: MCU Core – RISC-V RV32EC core @ 48MHz 32-bit hardware divider (HWDIV) Memory – Up to 32KB ILM-SRAM, up to 8KB DLM-SRAM Storage – 64KB program FLASH (APROM+BOOT), 1KB FLASH data area Peripherals Up to 46 I/Os 6x Enhanced PWM (EPWM) 1x I2C, 1x SPI/SSP, 2x UART Up to 20x 12-bit ADC up to 100Ksps Up to 20x 12-bit ADC up to 1.2 Msps Capture/compare/pulse width modulation for up […]

December 15, 2020December 15, 2020 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

BBC Dr Who HiFive Inventor Coding Kit review – Tynker visual programing and MicroPython

The BBC Doctor Who HiFive Inventor Coding Kit was announced at the end of November 2020 with the goal of teaching IoT to young kids. But one day, I noticed the postman left a package on the ground right next to my house’s gate for some reason. I had no idea what it could be until I read it was from SiFive on the package. So here I am about to review BBC Doctor Who HiFive Inventor Coding Kit! The package actually included two small packages with one being an “expansion board”… HiFive Inventor Coding Kit Unboxing We’ve already written about the specs in the announcement post, but here they are again for those who forgot it’s based on SiFive FE310 RISC-V microcontroller and ESP32 for WiFi and Bluetooth. Let’s open the thinner “expansion board” package first. It’s actually the HiFive Inventor board – aka the mainboard – that comes […]

December 15, 2020December 15, 2020 by Jean-Luc Aufranc (CNXSoft) - No Comments

Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures

Linus Torvalds has just released Linux 5.10: Ok, here it is – 5.10 is tagged and pushed out. I pretty much always wish that the last week was even calmer than it was, and that’s true here too. There’s a fair amount of fixes in here, including a few last-minute reverts for things that didn’t get fixed, but nothing makes me go “we need another week”. Things look fairly normal. It’s mostly drivers – as it should be – with a smattering of fixes all over: networking, architectures, filesystems, tooling.. The shortlog is appended, and scanning it gives a good idea of what kind of things are there. Nothing that looks scary: most of the patches are very small, and the biggest one is fixing pin mapping definitions for a pincontrol driver. This also obviously means that the merge window for 5.11 will start tomorrow. I already have a couple […]

December 10, 2020December 10, 2020 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

RISC-V hardware & software ecosystem highlights in 2020

The RISC-V Summit 2020 is currently taking place virtually, and RISC-V International, a non-profit corporation aiming to drive the adoption and implementation of the RISC-V instruction set architecture (ISA), took the occasion to remind us of the growth of the ISA both in terms of commercial adaption, education, and other projects. Calista Redmond, CEO of RISC-V International, detailed the growth in memberships: This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, SoCs, developer boards, software and tools across computing from embedded to enterprise … We’re proud of our growing global membership, which has more than doubled in the last year to 1,000 total members, including 222 organizations.” RISC-V also launched the RISC-V Exchange now listing over 124 RISC-V cores, SoCs, and developer boards, as well as 129 […]

December 8, 2020December 8, 2020 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Andes adds L2 cache, multi-core support to Linux capable RISC-V cores

Last year, Andes introduced the AndesCore 27-Series of Linux capable RISC-V cores with a vector processing unit for AI acceleration with specifically the 32-bit A27 and the 64-bit AX27 cores. The company also introduced the higher-end AndesCore 45-series (A45 and AX45) at about the same time, but we somehow missed the announcement. Andes has now added more Linux capable RISC-V AndesCore to the aforementioned families with the high-performance superscalar A45MP and AX45MP multi-core processors, and A27L2 and AX27L2 processors with an L2 cache controller. Andes A27L2 and AX27L2 cores Based on the highlights, the new cores look identical to the A27 and AX27L2 cores announced last year expect the additional L2 cache that comes with optional ECC. AndesCores A27L2 and AX27L2 key features and specifications: AX27L2 – 64-bit, 5-stage pipeline CPU architecture (RV64GCPN), enabling software to utilize the memory spaces far beyond 4GB A27L2 – 32-bit, 5-stage pipeline CPU architecture […]

November 26, 2020November 26, 2020 by Abhishek Jadhav - 3 Comments

DevTerm with ClockworkPi v3.14: a modular, portable computer

After the launch of ClockworkPi GameShell in Q4 2018, now ClockworkPi has come with yet another exciting product. DevTerm is a portable computer that comes with a 6.8-inch IPS screen, a keyboard with 67 keys, and a battery module, all connected to ClockworkPi v3.14 carrier board and a choice of core modules. It will also come with an optional built-in thermal printer. ClockworkPi v3.14 Mainboard and the Core boards The mainboard ClockworkPi v3.14 uses a compact design and comes with a reduced size of 95x77mm. With a modular design, it gives you a choice of “core board” modules for various applications. Moreover, ClockworkPi v3.14 is now compatible with the Raspberry Pi CM3 series, which means that your work on the Raspberry Pi can be “teleported” to a portable terminal without hassle. It has integrated 5GHz WIFI (802.11ac) and Bluetooth 5.0 which makes it suitable for wireless communication applications as well. […]

November 25, 2020 by Abhishek Jadhav - No Comments

M1108 AI accelerator chip delivers up to 35 TOPS for high-end edge AI applications

Last week, Mythic announced a breakthrough with compute-in-memory technology based on a 40 nm process with what the company claims to be the industry’s first Analog Matrix Processor. The M1108 AMP AI accelerator chip targets high-end edge AI applications including smart home, AR/VR, drones, and is said to set a benchmark in the industry for high performance and low power in a single cost-effective device, also available in M.2 and PCIe form factors. The M1108 comes with an array of flash cells, ADCs, a 32-bit RISC-V nano-processor, a SIMD vector engine, SRAM, and a high-throughput Network-on-Chip (NOC) router. With 108 AMP tiles, the M1108 provides up to 35 Trillion-Operations-per-Second (TOPS) enabling ResNet-50 at up to 870 fps. This enables a power-efficient execution of complex AI models such as ResNet-50, YOLOv3, and OpenPose Body25. The industry leader NVIDIA also has a similar AI accelerator chip NVIDIA Xavier AGX which delivers up […]