RISC-V open architecture allows designers to implement their own instructions, and some of those may become an official RISC-V extension. But the process to approve a new extension may have been suboptimal, so RISC-V International has just unveiled the Fast Track Architecture Extension Process, or Fast Track for short, that streamlines the ratification of small architecture extensions, as well as ZiHintPause, the first extension to be ratified under the new Fast Track process. The process is designed for simpler extensions that are uncontentious and offer value to the RISC-V community at large, so it’s not suitable for more complex extensions. An extension that has been submitted for consideration will undergo an internal review before entering a 45-day public review process. You can read detailed rules for the new extension ratified process here. The ZiHintPause extension went through this 45-day review process on Google Group, and was very recently ratified. The […]
Linux 5.11 Release – Main Changes, Arm, MIPS & RISC-V Architectures
Linus Torvalds has released Linux 5.11 just in time for… “Valentine’s Day”: Nothing unexpected or particularly scary happened this week, so here we are – with 5.11 tagged and pushed out. In fact, it’s a smaller-than-average set of commits from rc7 to final, which makes me happy. And I already have several pull requests lined up for tomorrow, so we’re all set for the merge window to start. But in the meantime – and yes, I know it’s Valentine’s Day here in the US – maybe give this release a good testing before you go back and play with development kernels. All right? Because I’m sure your SO will understand. Linus Last time around, Linux 5.10 was an LTS release that added EXT-4 performance enhancements, improved post-Spectre performance, as well as the enablement of BCM2711 (Raspberry Pi 4) display pipeline, among other many changes. Some of the notable changes in […]
Ingenic T40 4K Video & AI Vision Processor mixes MIPS & RISC-V cores with AI accelerator
Ingenic T31 MIPS & RISC-V AI video processor was introduced last year with the MIPS core including SIMD128 Vector instructions for deep learning. The Chinese company has now introduced the new Ingenic T40 processor still with MIPS and RISC-V cores, but also a dedicated 8 TOPS AI engine/CNN accelerator. The new processor is especially suited to smart AI vision application thanks to support for 4K cameras, and 4K MJPEG/H.264/H.265 hardware video encoding, complemented by the 8 TOPS AI engine for computer vision workloads such as people detection, face recognition, object detection, and so on. Ingenic T40 key features and specifications: CPU – Dual-core MIPS XBurst2 @ 1.2 GHz with 256KB L2 Cache, SIMD512 instruction set MCU – 600MHz RISC-V coprocessor AI Engine – 8 TOPS neural network accelerator with 1MB memory pool, support for int16/int8/int4/int2 convolution width Memory – DDR2/DDR3/DDR3L up to 2GB Storage – SPI NOR flash, SPI NAND flash, […]
FOSDEM 2021 Online February 6-7 – Hardware, Embedded & IoT talks
FOSDEM is an open-source developer event that takes place on the first week-end of February every year in Brussels, Belgium. Every year except this year, as due to COVID-19 restrictions, FOSDEM 2021 will take place online like most events these days. The schedule has been up for some time, and today I’ll look at some of the interesting talks mostly from the Embedded, Mobile and Automotive “virtual devroom” but also other tracks. Saturday, February 6, 2021 13:00 – 14:00 – From Reset Vector to Kernel – Navigating the ARM Matryoshka Long gone are the times of executing the OS in-place from memory-mapped flash upon reset. A modern SoC now comes with complex mask ROM firmware, with driver, filesystem, protocol and crypto support for loading… yet another bootloader. In his talk, Ahmad follows this chain of bootloaders until the kernel is started, stopping along the way for RAM setup, peripherial initialization, […]
Android 10 ported to RISC-V board powered by Alibaba T-Head XuanTie C910 Processor
RISC-V has made a lot of progress in just a few years, but for anything requiring 3D graphics acceleration, it’s not quite there yet. and we only expect RISC-V SoC with Imagination Technologies GPU to come out later this year on hardware such as BeagleV SBC. An OS that will definitely require 3D graphics acceleration is Android, and work has already started since T-Head, a business entity of Alibaba Group specializing in semiconductor chips, has already ported Android 10 (AOSP) on RISC-V architecture with support for graphics and the touchscreen display. The demo above runs on ICE EVB powered by a XuanTie C910 based high-performance SoC board developed by T-Head. Specifically, the ICE SoC integrates two XuanTie C910 cores (RV64) @ 1.2 GHz, one other XuanTie C910V core @ 1.2 GHz with vector extensions, a single-core 3D GPU core [Update: it’s a Vivante GC8000UL GPU], DDR4 memory support, a GMAC […]
Pine64 mailbag – PinePhone postmarketOS Edition, PineCone BL602 board, and Pinecil soldering iron
Pine64 community was pretty busy last year with the launch of several products. Recently I’ve received a couple of packages with some of those products, namely PinePhone Community Edition: PostmarketOS, PineCone WiFi & BLE IoT board based on BL602 RISC-V SoC, and Pinecil soldering iron also based on a RISC-V chip for control, but this time GD32V generic-purpose MCU. I’ll most show what I have received without going into too many details, except for PinePhone which I have already set up and used for one hour or so. PineCone BL602 board I received PineCone at the end of last year in a separate envelope with the board only. There’s not much to it with the BL602 processor offering WiFI and Bluetooth, a USB-C port for programming and power, and a few I/Os. The board is interesting as it is the first RISC-V IoT board with wireless connectivity built into the […]
$119+ BeagleV powerful, open-hardware RISC-V Linux SBC targets AI applications
Running Linux on RISC-V hardware is already possible, but you’d have a choice of low-end platforms like Kendryte K210 that’s not really practical for anything, or higher-end board like SiFive HiFive Unmatched or PolarBerry for which you’d have to spend several hundred dollars, or even over one thousand dollars to have a complete system. So an affordable, usable RISC-V Linux SBC is clearly needed. We previously wrote about an upcoming Allwinner RISC-V Linux SBC that will be mostly useful for camera applications without 3D GPU, and a maximum of 256MB RAM. But today, we have excellent news, as the BeagleBoard.org foundation, Seeed Studio, and Chinese fabless silicon vendor Starfive partnered to design and launch the BeagleV SBC (pronounced Beagle Five) powered by StarFive JH7100 dual-core SiFive U74 RISC-V processor with Vision DSP, NVDLA engine, and neural network engine for AI acceleration. BeagleV specifications: SoC – StarFive JH7100 Vision SoC with: […]
Year 2020 in review – Top ten posts and stats
It’s this time of the year when we look back at what happened, and what may be next. 2020 did not pan out as planned in more ways than one, but there were still some interesting developments. Based on 2019 announcements, 2020 was promising to be an exciting year for Amlogic and Rockchip with the expected launch of RK3588 and S908X high-end processors for 8K capable devices, but we’ll have to wait for 2021 for this to happen. Instead, the most interesting processor of the year from the Allwinner, Amlogic, and Rockchip offerings was probably Amlogic S905X4 processing adding AV1 hardware decoding. As pointed out in our “RISC-V 2020 highlights” post, it was a fairly eventful year for RISC-V architecture, although there’s still a long road ahead, especially for application processors. We had seen some general-purpose and Bluetooth RISC-V MCUs in 2019, but 2020 saw the launch of the first […]