risc-v News - Page 33 of 51 - CNX Software

June 28, 2021 by Jean-Luc Aufranc (CNXSoft) - 13 Comments

Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards

Let’s a lot of excitement around RISC-V open architecture, but a lot of work still needs to be done to bring the ecosystem to level with Arm or x86 architecture from the silicon to the software. Progress is made step-by-step and one of these steps is Canonical released Ubuntu 64-bit RISC-V (RISCV64) images for some of SiFive HiFive boards, as well as QEMU open-source emulator. Specifically, Canonical released an Ubuntu 20.04.2 LTS image for HiFive Unleashed & QEMU, and an Ubuntu 21.04 image for HiFive Unleashed, HiFive Unmatched, and QEMU. Note those are only server images, and there’s no desktop image yet like for Ubuntu 21.04 on Raspberry Pi 2/3/4. It’s been possible to run RISC-V Linux in QEMU for at least three years, but when I tried it was a minimal system based on Busybox, so let’s try again with Ubuntu 21.04 following the instructions provided on Discourse. I […]

June 23, 2021June 24, 2021 by Jean-Luc Aufranc (CNXSoft) - 22 Comments

SiFive Performance P550 is the fastest 64-bit RISC-V processor so far

SiFive Performance P550 fastest RISC-V processor

SiFive has announced two RISC-V “Performance” cores with Performance P550 that should be the fastest 64-bit RISC-V processor so far with a SPECInt 2006 score of 8.65/GHz, as well as a Performance P270 Linux capable processor with full support for the RISC-V vector extension v1.0 rc. SiFive Performance P550 P550 highlights: RISC-V RV64GBC ISA 13 stage, 3-issue high-performance out-of-order pipeline Supports multicore coherence with up to 4 cores in a core complex Private 32KB+32KB L1 cache and a private 256KB L2 cache per core Up to 4MB L3 cache in a four-core cluster SPECint 2006 – 8.65/GHz 2.4 GHz in 7nm with a footprint of less than 0.25 mm SiFive compares the Performance P550 core to Arm’s Cortex-A75 with higher performance in SPECint2006 and SPECfp2006 integer/floating-point benchmark, all a much smaller area which would enable a quad-core P550 cluster on about the same footprint as a single Cortex-A75 core. There […]

June 21, 2021June 23, 2021 by Jean-Luc Aufranc (CNXSoft) - 15 Comments

$3.5 RV-Debugger Plus UART & JTAG debug board comes with BL702 Zigbee & BLE RISC-V SoC

USB to UART debug boards are a necessity for anyone playing with single board computers, at least when using bleeding-edge bootloader or Linux kernel where the target board may not always boot, or when troubleshooting booting problems. Those are often based on FDTI or WCH chips, but Sipeed RV-Debugger Plus features Bouffalo Lab BL702 Zigbee & Bluetooth LE RISC-V SoC instead and offers both UART and JTAG interfaces. So let’s have a look at both the board and SoC. Sipeed RV-Debugger Plus USB to TLL debug boards are meant to be simple and that’s the case for Sipeed latest BL702 board as it comes with a 12-pin connector with Tx/Rx for UART, 8 signals for JTAG, plus 5V, 3.3V, and GND power signals. We can also see pads for Tx/Rx/CTS, a boot button, a crystal oscillator, and a USB-C port to connect to the host computer. What I don’t see […]

May 20, 2021May 21, 2021 by Jean-Luc Aufranc (CNXSoft) - 49 Comments

Nezha RISC-V Linux SBC launched for $99 and up

Last month, we wrote about Allwinner D1 SBC & processor that promised to offer a relatively low-cost RISC-V Linux solution. We were not given a name at the time, but there was a logo of Nezha, a fictional character from Chinese literature. The board is now known as the Nezha SBC and has been launched on Indiegogo for $99 and up as a board designed for IoT projects running Linux, but can also be purchased directly on Aliexpress for the same price. [Update: It can also be purchased on Taobao for 599 RMB] Nezha SBC specifications: SoC – Allwinner D1 single-core XuanTie C906 64-bit RISC-V processor @ 1.0 GHz with HiFi4 DSP, G2D 2D graphics accelerators Memory – 1GB DDR3 memory Storage – 256MB SPI NAND flash, MicroSD card slot Video Output – HDMI 1.4 port up to 4Kp30, MIPI DSI & touch panel interface up to 1080p60 Decoding – […]

May 3, 2021May 4, 2021 by Jean-Luc Aufranc (CNXSoft) - 11 Comments

RISC-V International to give away 1,000 RISC-V development boards

The best way for a new platform to get good software support is to bring hardware into the hands of developers. That’s exactly what RISC-V International is doing by inviting developers to sign up for a RISC-V developer board sponsored by RISC-V and contributing members. There are 1,000 boards on offer with 1GB to 16GB RAM depending on the target project from five companies and organizations namely Allwinner, Beagleboard.org, SiFive, Microchip Technology (previously Microsemi), and RIOS. Here are the stated goals of the giveaway: Spur innovation Enable new opportunities for the next generation of developers to work with the RISC-V ISA Provide a platform For testing To write programs that run on RISC-V Develop software Integrate existing software stacks Optimize ecosystem software Share feedback on the product such as ease to integrate software stacks, develop and test extensions, etc. The company did not provide an exact list of development board […]

May 2, 2021May 10, 2021 by Jean-Luc Aufranc (CNXSoft) - 19 Comments

Allwinner D1 RISC-V processor SDK & Documentation

We published information about Allwinner D1 SBC and processor a few weeks ago. The news was pretty interesting as it’s the first RISC-V processor from the company, and one of the first affordable RISC-V SBC. But all we had at the time was hardware information from a leak, or rather from China-only Allwinner developer website. But now the company has added more information to its open-source development website with the release of documentation, now only in Chinese, as well as the Allwinner D1 Tina SDK. Eventually, there should be a better SDK via linux-sunxi community and some are already working on the Allwinner D1 SBC, but let’s try to get the SDK from Allwinner and build the code from source using the documentation. First, you’d need to register on Allwinner open-source website and click on signup. You’ll probably want to select Email registration. Now fill your username, select a country, […]

April 30, 2021April 30, 2021 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Antmicro ARVSOM offers StarFive JH71x0 RISC-V processor, Raspberry Pi CM4 compatibility

The Linux capable BeagleV SBC, now called “BeagleV Starlight”, was announced last January with a StarFive JH7100/JH7110 64-bit RISC-V processor, and developers and beta users have just started to get their hand on the board in recent days. But there’s another StarFive JH71x0 hardware in the works with Antmicro ARVSOM. The system-in-module will feature the dual-core RISC-V processor, and be compatible with Raspberry Pi CM4, and by extension Antmicro’s Scalenode server-oriented baseboard. The company did not provide the complete specifications for the module, but based on public information available, Antmicro ARVSOM should feature the following: SoC – StarFive JH7100 Vision SoC: RISC-V U74 dual-core with 2MB L2 cache @ 1.5 GHz Vision DSP Tensilica-VP6 for computing vision NVDLA Engine 1 core (configuration 2048 MACs @ 800MHz – 3.5 TOPS) Neural Network Engine (1024MACs @ 500MHz – 1 TOPS) VPU – H.264/H.265 decoder up to 4Kp60, dual-stream decoding up to 2Kp30 […]

April 27, 2021April 27, 2021 by Jean-Luc Aufranc (CNXSoft) - 7 Comments

SiFive Intelligence X280 64-bit RISC-V processor integrates AI extensions

The last RISC-V core announced by SiFive was the U8-Series out-of-order RISC-V Core IP that aims to compete against Arm Cortex-A72 Core. But in their latest announcement, the company built upon the 64-bit RISC-V U7-series with the SiFive Intelligence X280 multi-core, Linux capable RISC-V processor adding vector extensions and SiFive Intelligence Extensions, and optimized for AI/ML compute at the edge. SiFive Intelligence X280 key features: 64-bit RISC-V ISA with 8-stage dual-issue in-order pipeline, coherent multi-core, Linux capable based on U7 series core. SiFive Intelligence Extensions for ML workloads – BF16/FP16/FP32/FP64, int8 to 64 fixed-point data types 512-bit vector register length – Variable-length operations, up to 512-bits of data per cycle High-performance vector memory subsystem Memory parallelism provides cache miss tolerance Virtual memory support with precise exceptions Up to 48-bit addressing SiFive Intelligence includes software solutions to leverage the X280’s features and provide “great AI inference performance” using TensorFlow Lite. No […]