ESP32-H2 Bluetooth LE & 802.15.4 RISC-V SoC shows up in ESP-IDF source code

ESP32-H2

Espressif Systems is working on yet another RISC-V chip with ESP32-H2 SoC offering Bluetooth LE and 802.15.4 connectivity showing up in the ESP-IDF framework source code. A code comparison shows ESP32-H2 is very similar to ESP32-C3 with a single RISC-V core, albeit clocked at up to 96 MHz, and the first Espressif SoC without WiFi, as the WiFi radio is replaced with an 802.15.4 radio for Thread, Zigbee, etc… that can be used for the development of Home Automation, Smart Lighting, and wireless sensor network applications. While looking at the source code differences between ESP32-C3 and ESP32-H2, the really only major differences were the 802.15.4 radio and lower maximum frequency, and at the current time, it looks like most of the rest is unchanged, so it’s possible they kept the same amount of RAM (400KB), storage, and most of the same peripherals, but it could just well be the code […]

WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA

WARP-V CPU Core Generator

If you have been working on open standard RISC-V ISA CPU cores, there is a high chance that you have come across WARP-V. For newbies, WARP-V is a RISC-V CPU core generator written in TL-Verilog (Transaction-Level Verilog) that supports not only RISC-V but also MIPS ISA. WARP-V has been in discussion for a while due to its unparalleled architectural scalability in a small amount of code. The famous proverb “Necessity is the mother of invention” applies to the invention of TL-Verilog and with that this WARP-V CPU core generator. For decades, hundreds of engineers have been working on designing a single CPU core that was more complex in the race to achieve higher single-core performance. But with recent developments in the semiconductor industry, developer and engineer Steve Hoover, with decades of experience in designing CPU cores, has come up with the idea of developing a WARP-V core in just 1.5 […]

ESP32-C3 board comes with 16340 battery holder, D1 mini compatibility

LilyGO TTGO T-OI Plus

It looks like ESP32-C3 floodgates have opened. We’ve just written about several NodeMCU ESP32-C3 boards, and now there’s another board with the RISC-V WiFI & Bluetooth processor. Meet LilyGo TTGO T-OI PLUS equipped with a 16340 battery holder. Getting a battery-powered ESP32-C3 board could prove to be very interesting as ESP32-C3 power consumption is much lower than ESP8266 and ESP32, notably in deep sleep mode, where the RISC-V processor consumes just 5uA, against 20 uA for ESP8266 and ESP32, and the difference is even greater in light sleep mode (ESP8266: 2000 uA vs ESP32-C3: 130 uA). LilyGo TTGO T-OI PLUS specifications: SoC – Espressif Systems ESP32-C3 single-core RISC-V processor @ 160 MHz with 2.4 GHz WiFi, Bluetooth 5.0 LE Storage – TBD flash (probably 2MB or 4MB) Antenna – Ceramic antenna and IPEX connector USB – USB-C port for power and programming Expansion 2x 8-pin headers with 12x GPIO, 1x […]

NodeMCU ESP32-C3 WiFi & BLE IoT boards show up for about $4

ESP-C3-01-M developmentkit

ESP32-C3 RISC-V IoT processor with 2.4 WiFI and Bluetooth LE 5.0 was unveiled in December 2020, and Espressif Systems’ own ESP32-C3-DevKitM-1  board has been available in limited quantities as an “engineering sample”. But now I’ve noticed third-party NodeMCU ESP32-C3 boards are being sold on Aliexpress for around $4 with ESP32-C3S_Kit and ESP-C3-01M-Kit both based on AI Thinker ESP32-C3 modules announced a few months ago. NodeMCU ESP32-C3S_KIt Specifications: Wireless module – AI Thinker ESP32-C3S (footprint compatible with ESP32-S / ESP32-WROOM-32D) with ESP32-C3 RISC-V processor @ 160 MHz, 2.4 GHz WiFi, Bluetooth 5.0 LE, 4MB flash, on-board PCB antenna, and IPEX connector (which may be soldered or not). USB – Micro USB port for power and programming via CH340C USB to TTL chip Expansion – 2x 15-pin headers with GPIO, SPI, UART, ADC, I2S, 3.3V, GND Misc – RGB LED, Reset key, user-programmable key Dimensions – 49 x 26 mm ESP32-C3S_Kit is […]

Embedded development board features Microchip PolarFire RISC-V FPGA SoC

PolarFire RISC-V FPGA SoC development board

Microchip/MicroSemi first introduced PolarFire RISC-V FPGA SoC at the end of 2018, with the chip being like the RISC-V equivalent of Xilinx Zynq Ultrascale+ Arm & FPGA MPSoC. The following year, ARIES Embedded unveiled the ARIES M100PF system-on-module and evaluation board, before Microchip launched PolarFire SoC Icicle 64-bit RISC-V and FPGA development board, followed by the more compact PolarBerry SBC in 2020. There’s now at least a fourth platform based on PolarFire SoC with Aldec TySOM-M-MPFS250 embedded development board.   Aldec TySOM-M-MPFS250 specifications: SoC – Microchip PolarFire MPFS250T-FCG1152 SoC  with 4x SiFive U54 RV64GC application cores (similar to Cortex-A35 performance), 1x SiFive E51 RV64IMAC monitor core, FPGA fabric with 254K logic cells, 17.6 Mb RAM System Memory 2GB (16Gbit) 32-bit DDR4 for the FPGA 2GB (16Gbit) 36-bit RAM with ECC for the RISC-V cores (aka MSS = Microprocessor Subsystem) Storage – MicroSD card socket, eMMC flash, SPI flash, 64 Kbit […]

Kendryte K510 tri-core RISC-V AI processor deliver up to 3 TOPS

Kendryte K510 Block Diagram

Kendryte K510 is a 64-bit tri-core RISC-V processor clocked at up to 800 MHz with AI accelerators that succeed the 400 MHz Kendryte K210 dual-core RISC-V AI processor released a few years ago first in Kendryte KD233 board, and then boards like Maxduino or Grove AI HAT conveniently programmable with Arduino or Micropython. Canaan formally announced the processor yesterday at the 2021 World Artificial Intelligence Conference claiming K510 had three times the performance of K210 making it suitable for UAV high-definition aerial photography, high-definition panoramic video conferences, robotics, STEAM education, driver assistance scenarios, and industrial and professional cameras. The press release did not have much information, but multiple sources provided additional details to CNX Software, so we have Kendryte K510 specifications: Processor – 2x 64-bit RISC-V processor @ 800 MHz, and 1x 64-bit RISC-V core @ 800 MHz with DSP extension AI subsystem with 3 TOPS in total KPU: General […]

XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76

XiangShan RISC-V architecture

SiFive Performance P550 was supposed to be the most powerful RISC-V core to date, capable of outperforming Arm’s Cortex-A75 core in raw performance, but especially in terms of efficiency, with three times the performance per mm2. But there may be an even more powerful RISC-V processor, albeit developed as a research project, with the Chinese Academy of Science (CAS)’s XiangShan open-source processor presented at the recent RISC-V World Conference China 2021 with the goal of matching Cortex-A76 performance. The project was launched on June 11, 2020, and 25 classmates and teachers participated in the development of Xiangshan with 821 main branch code mergers, 3296 code submissions, more than 50,000 lines of code, and more than 400 documents, mostly in Chinese only for now. This culminated with an 8-core prototype built based on Yanqihu (雁栖湖) architecture using TSMC’s 28nm process with the processor running up to 1.2 or 1.3 GHz that […]

Linux 5.13 Release – Notable changes, Arm, MIPS and RISC-V architectures

Linux 5.13 release

Linus Torvalds has just announced the release of Linux 5.13: So we had quite the calm week since rc7, and I see no reason to delay 5.13. The shortlog for the week is tiny, with just 88 non-merge commits (and a few of those are just reverts). It’s a fairly random mix of fixes, and being so small I’d just suggest people scan the appended shortlog for what happened. Of course, if the last week was small and calm, 5.13 overall is actually fairly large. In fact, it’s one of the bigger 5.x releases, with over 16k commits (over 17k if you count merges), from over 2k developers. But it’s a “big all over” kind of thing, not something particular that stands out as particularly unusual. Some of the extra size might just be because 5.12 had that extra rc week. And with 5.13 out the door, that obviously means […]

EmbeddedTS embedded systems design