A little while ago, I wrote about WCH CH32V307 32-bit RISC-V MCU that was found in a board with eight UART ports that could be controlled over Ethernet or USB, and the company has released some source code to use the board while inviting the community to submit pull requests to the project. But now WCH, RT-Thread, LCSC, and EasyEDA have joined hands to launch the RISC-V design challenge where the companies will provide a free board or two RISC-V chips to selected participants, as well as cash prizes with up to $1000 offered to the best projects. The companies have prepared 300 boards and 200 chips for this contest. All you need to do to get a chance to get either one CH32V307V-EVT-R1 development board or two CH32V307 RISC-V microcontrollers is to enter your contact and project details in this Google form by April 30, 2022. The conditions are […]
RISC-V or Arm? This tiny 4x4cm Linux board with WiFi offers both options
Last fall, we wrote about Allwinner D1s/F133-A RISC-V processor and the upcoming MangoPi MQ1, a tiny 4x4cm board based on the processor. The board is not for sale, but we have more details, and the company is also working on an Arm version equipped with Allwinner T113-S3 dual-core Cortex-A7 processor that is pin-to-pin compatible with F133-A SoC. The Allwinner F133-A board will finally be called MangoPi Nezha-MQ, or MangoPi MQ for shorts, and come with 64MB on-chip RAM while the Allwinner T113-S3 board, with 128MB on-chip RAM, will be named MangoPi MQ-Dual. Both are fitted with a Realtek RTL8189-based Wi-Fi module, offer display and camera interfaces, two USB-C interfaces, and headers for GPIOs. MangoPi MQ RISC-V or Arm Linux board MangoPi MQ/MQ-Dual specifications: SoC (one or the other) MangoPi MQ – Allwinner D1s/F133-A 64-bit RISC-V processor @ 1 GHz with 64 MB DDR2 MangoPi MQ-Dual – Allwinner T113-S3 32-bit dual-core […]
CLEAR is an open-source FPGA ASIC provided by Efabless’ chipIgnite
Open-source SoC designs are available to run on FPGA hardware, but few make it to silicon due to the costs involved. That’s why a couple of years ago the Google SkyWater PDK (process design kit) was released together with an offer to manufacture up to 100 pieces for free to selected designs in collaboration with Efabless. Efabless chipIgnite is an evolution of that offer with $9,750 being enough funds to manufacture 100 QFN or 300 WCSP parts, or alternatively 1,000 parts for $20 each ($20,000). Based on the company’s Caravel template SoC and the openFPGA generator framework, CLEAR open-source FPGA ASIC design is meant to promote and demonstrate the chipIgnite “paid IC creation” solution. You can participate by joining a group buying campaign on GroupGets to get a development board based on CLEAR for $74.99 plus shipping. CLEAR open-source FPGA ASIC features: FPGA – Small 8×8 (64) CLB eFPGA CPU […]
Intel to invest $1 billion in foundry innovation, becomes RISC-V International member
Intel has just announced a $1 billion fund to support companies bringing innovations and new technologies to the foundry ecosystem. The company says the fund will prioritize investments in “capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, innovative chip architectures, and advanced packaging technologies.” What’s interesting is that it does not only cover x86 architecture but also Arm and RISC-V, with a focus on the latter, as Intel has just become a Premier member of RISC-V International, and partnered with several companies offering RISC-V solutions including Andes Technology, Esperanto Technologies, SiFive, and Ventana Micro Systems. Intel’s Open Chiplet Platform Part of the investment will go to the Open Chiplet Platform offering a modular approach to chip design through chiplets with each block/chiplet customized for a particular function. This will allow designers to select the best IP and process technologies for a particular SoC. […]
India goes RISC-V with VEGA processors
One of the main advantages of RISC-V architecture is that it is open, so any organization with the right skills can develop its own cores, and India’s government has taken up this opportunity with the Microprocessor Development Programme (MDP) helping develop VEGA RISC-V cores locally. Thanks to funding by the Ministry of Electronics and Information Technology (MeitY), the Centre for Development of Advanced Computing (C-DAC) managed to design five RISC-V processors ranging from a single-core 32-bit RISC-V microcontroller-class processor to a Linux capable quad-core 64-bit out-of-order processor. Key features of the five VEGA cores developed by the C-DAC: VEGA ET1031 – 32-bit single-core 3-stage in-order RV32IM processor with AHB/AXI4.bus, optional MMU, optional Debug VEGA AS1061 – 64-bit single-core 6-stage in-order RV64IMAFDC processor with 8KB D-cache, 8KB I-cache, FPU, AHB/AXI4 bus VEGA AS1161 – 64-bit single-core 16-stage pipeline out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, FPU, AHB/AXI4/ACE bus VEGA AS2161 […]
Golioth IoT development platform offers Zephyr SDK, support for nRF9160, ESP32, and over 100 other platforms
There are already plenty of IoT development platforms, but here’s another one with Golioth that relies on a Zephyr SDK, “first-tier” support for Nordic Semiconductor nRF9160 (cellular) and Espressif Systems ESP32-C3 (WiFi), as well as a QEMU-based simulator for easy testing. The use of an open-source Zephyr SDK even enables them to support over 100+ hardware components, and the company, also called Golioth, says their platform scales from one device for evaluation to one million devices during deployment, thanks notably to a free Dev Tier account to get started at no cost. Some of the other highlights of Golioth include: “Secure by Default” communication over efficient protocols like CoAP and soon MQTT Access to Device Services like Software updates that include secure boot and firmware management Real-time NoSQL database (LightDB) that can be useful for creating Digital Twins and synchronization Time-series database (LightDB Stream) for storing and querying sensor data […]
WCH CH32V307 RISC-V development board features 8 UART ports controlled over Ethernet
CH32V307V-EVT-R1 is a development board based on WCH CH32V307 RISC-V microcontroller with an Ethernet port, an USB Type-C port, and eight UART interfaces accessible through headers. As we noted in our article about CH583 Bluetooth 5.3 RISC-V microcontroller, WCH (Jiangsu Qin Heng) has started to share resources like datasheets and code samples through Github. They’ve done the same again for CH32V307 with schematics (PDF only), a datasheet in English, and firmware either bare metal or based on RT-Thread OS to control the eight serial interfaces over Ethernet. Let’s check CH32V305 and CH32V307 MCU specifications first: MCU core – WCH designed RISC-V4F 32-bit RISC-V core up to 144MHz FPU – Single-cycle multiplication and hardware division, hardware float point unit (FPU) ; Memory – Up to 64KB SRAM Storage – Up to 256KB Flash Networking – Gigabit Ethernet MAC, 10 Mbps PHY USB – 1x USB 2.0 OTG full-speed interface, 1x USB […]
Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals
Tang Nano 9K FPGA is the third board from Sipeed based on GOWIN FPGA following the original Tang Nano board with 1K LUT and Tang Nano 4K launched last year with GW1NSR-LV4C (aka GW1NSR-4C) FPGA offering 4068 logical units and 64 Mbit PSRAM, plus an Arm Cortex-M3 hard processor. As its name implies, the new board comes with 9K LUTs, as well as 64 Mbit PSRAM, 32 Mbit Flash, a micro SD card, and video I/O (HDMI, RGB LCD connector) that makes it suitable to run Verilog HDL code emulating a PicoRV32 RISC-V soft-core with all peripherals. Tang Nano 9K FPGA board specifications: FPGA – GOWIN LittleBee GW1NR-9/GW1NR-LV9 8,640 logical units (LUTs) 6,480 flip-flop 17,280 bits shadow SRAM (SSRAM) 486 Kbit block SRAM (BSRAM) 64 Mbit PSRAM 608 Kbit user flash 2x PLL Up to 276x user I/O Storage – 32 Mbit SPI flash. MicroSD card socket Display I/F HDMI […]