risc-v News - Page 19 of 52 - CNX Software

December 14, 2022 by Jean-Luc Aufranc (CNXSoft) - 18 Comments

Sipeed LM4A – T-Head TH1520 RISC-V module to power Raspberry Pi 4 competitor and cluster board

Sipeed LM4A is a quad-core RISC-V system-on-module based on the T-Head TH1520 SoC found in the ROMA laptop and destinated to be found in a Raspberry Pi SBC competitor as well as a cluster board. The LM4A, which stands for Lichee Module 4 Model A, comes with 4GB to 16GB RAM, and up to 64GB flash, and connects to the carrier board through a 260-pin SO-DIMM connector. The TH1520 is one of the rare RISC-V SoCs with a 3D GPU, and the SBC based on LM4A has been shown to outperform the Raspberry Pi 4 in benchmarks as we’ll see below. Sipeed LM4A specifications: SoC – Alibaba T-Head TH1520 quad-core RISC-V Xuantie C910 (RV64GCV) processor @ 2.5 GHz, Xuantie C906 audio DSP @ 800 MHz, low power Xuantie E902 core, 50 GFLOPS Imagination 3D GPU, and 4 TOPS NPU System Memory – 4GB, 8GB, or 16GB RAM Storage – Optional […]

December 13, 2022February 20, 2023 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Linux 6.1 LTS release – Main changes, Arm, RISC-V and MIPS architectures

Linus Torvalds announced the release of Linux 6.1, likely to be an LTS kernel, last Sunday: So here we are, a week late, but last week was nice and slow, and I’m much happier about the state of 6.1 than I was a couple of weeks ago when things didn’t seem to be slowing down. Of course, that means that now we have the merge window from hell, just before the holidays, with me having some pre-holiday travel coming up too. So while delaying things for a week was the right thing to do, it does make the timing for the 6.2 merge window awkward. That said, I’m happy to report that people seem to have taken that to heart, and I already have two dozen pull requests pending for tomorrow in my inbox. And hopefully I’ll get another batch overnight, so that I can try to really get as […]

December 6, 2022 by Jean-Luc Aufranc (CNXSoft) - 14 Comments

Armbian 22.11 released with 64-bit RISC-V UEFI, ultra minimal images support

Armbian 22.11 has just been released with three new SBCs, support for 64-bit RISC-V UEFI, a new ultra-minimal image optimized for software development, and various improvements. Armbian was born as a framework to build better OS images, usually Debian or Ubuntu, for Arm-based single board computers from Orange Pi, Hardkernel (ODROID), FriendlyElec, Banana Pi, and others, but now with the release of Armbian 22.11, support for the RISC-V architecture has started since the system can now generate 64-bit RISC-V UEFI images. Some other highlights of Armbian 22.11 include: Added support for Banana Pi BPI-M5 (Amlogic S905X3), ODROID-M1 (Rockchip RK3568), and Rock Pi 4C Plus (Rockchip RK3399-T) Enabled community images with a weekly release cycle Added ultra minimal images optimized for software deployment Improved support for the Rock Pi S (Rockchip RK3308) Kernel upgrade is frozen by default to improve stability I could not find details about the new “Minimal” images, […]

December 2, 2022December 2, 2022 by Jean-Luc Aufranc (CNXSoft) - 75 Comments

$6 Pine64 Ox64 SBC features BL808 64-bit/32-bit RISC-V multi-protocol WiSoC with 64MB RAM

Pine64 Ox64 is a single board computer powered by Bouffalo Lab BL808 dual-core 64-bit/32-bit RISC-V processor with up to 64MB embedded RAM, multiple radios for WiFi 4, Bluetooth 5.0, and 802.15.4 (Zigbee), as well as an AI accelerator. The board also features up to 16MB XSPI NOR flash, a MicroSD card socket, a USB 2.0 OTG port with support for a 2-lane MIPI CSI camera module, and two 20-pin GPIO headers for expansion. It measures just 51 x 21mm, or in other words, is about the size of a Raspberry Pi Pico W. Pine64 Ox64 specifications: SoC – Bouffalo Lab BL808 with: CPU Alibaba T-head C906 64-bit RISC-V core @ 480MHz Alibaba T-head E907 32-bit RISC-V core @ 320MHz Alibaba T-head E902 32-bit RISC-V @ 150MHz Memory – 728KB SRAM, 64MB embedded DRAM AI accelerator – NPU BLAI-100 (Bouffalo Lab AI engine) for video/audio detection/recognition Wireless 2.4 GHz 802.11 b/g/n […]

November 14, 2022November 18, 2022 by Jean-Luc Aufranc (CNXSoft) - 20 Comments

Sipeed M1s & M0sense – Low-cost BL808 & BL702 based AI modules (Crowdfunding)

Sipeed has launched the M1s and M0Sense AI modules. Designed for AIoT application, the Sipeed M1s is based on the Bouffalo Lab BL808 32-bit/64-bit RISC-V wireless SoC with WiFi, Bluetooth, and an 802.15.4 radio for Zigbee support, as well as the BLAI-100 (Bouffalo Lab AI engine) NPU for video/audio detection and/or recognition. The Sipeed M0Sense targets TinyML applications with the Bouffa Lab BL702 32-bit microcontroller also offering WiFi, BLE, and Zigbee connectivity. Sipeed M1s AIoT module The Sipeed M1S is an update to the Kendryte K210-powered Sipeed M1 introduced several years ago. Sipeed M1s module specifications: SoC – Bouffalo Lab BL808 with CPU Alibaba T-head C906 64-bit RISC-V (RV64GCV+) core @ 480MHz Alibaba T-head E907 32-bit RISC-V (RV32GCP+) core @ 320MHz 32-bit RISC-V (RV32EMC) core @ 160 MHz Memory – 768KB SRAM and 64MB embedded PSRAM AI accelerator – NPU BLAI-100 (Bouffalo Lab AI engine) for video/audio detection/recognition delivering up […]

November 4, 2022November 4, 2022 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

T-Head XuanTie C908 RISC-V core targets AIoT applications

We’ve seen two announcements of high-end RISC-V cores this week with the SiFive P670 and Andes AX65 processors each with a 4-way out-of-order pipeline, but Alibaba’s T-Head Semiconductor Xuantie C908 is a little different with a dual-issued, 9-stage in-order pipeline and support for the RISC-V Vector extension acceleration targeting mid-range AIoT applications. The C908 64-bit RISC-V core adopts the RV64GCB[V] instruction and complies with the RVA22 profile for better compatibility with Android and other “rich” operating systems. The company says its performance is between the C906 and C910 cores introduced in 2020 and 2019 respectively. XuanTie C908 highlights: RV32GCB[V] 32-bit and RV64GCB[V] 64-bit RISC-V architectures with Bit manipulation and (optional) Vector operations extensions Support for RV32 COMPAT mode which allows for 64-bit RISC-V CPUs to run 32-bit binary code, and was merged into Linux 5.19. XuanTie extensions, including Instruction, Memory Attributes Extension (XMAE). RVA22 profile compatibility Cluster of 1 to […]

November 3, 2022 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications

Andes Technology has unveiled the high-end AndesCore AX60 series out-of-order 64-bit RISC-V processors at the Linley Fall Processor Conference 2022 with the new cores designed for compute-intensive applications such as advanced driver-assistance systems (ADAS), artificial intelligence, augmented/virtual reality, datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage. AndesCore AX65 is the first member of the family and supports RISC-V scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar core with Out-of-Order (OoO) execution in a 13-stage pipeline and can fetch 4 to 8 instructions per cycle. The company further explains the AX65 core then decodes, renames, and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. The AX65’s memory subsystem also includes split 2-level TLBs (translation lookaside buffers) with up to 64 outstanding load/store instructions. Up to eight AX65 cores (or should that then be […]

November 2, 2022November 3, 2022 by Leo Zachary - 13 Comments

DongshanPI-D1s – An Allwinner D1s RISC-V development board designed to teach programming

The DongshanPI-D1s development board is comprised of a soldered-on Allwinner D1s RISC-V system-on-module board (SoM) and a carrier board with two 40-pin headers and a 2.0mm dedicated header. This development board is specifically designed to teach programming with a focus on the RISC-V architecture. The development board was designed by 100ask. They previously designed the Dongshan NeZha STU a development board based on the Allwinner D1. The main difference between the two is that 100ask did not include the Ethernet and HDMI interfaces on the DongshanPI-D1s board. The pinout of the headers is also slightly different because they opted to make the headers compatible with the widely used 40-pin GPIO from Raspberry Pi single board computers. DongshanPI-D1s preliminary specifications: D1s Core Lite SoC – Allwinner D1s single-core XuanTie C906 64-bit RISC-V processor @ 1.0 GHz with with 32 KB I-cache + 32 KB D-cache Memory – 64 MB DDR2 (SIP) […]