mips News - Page 9 of 19 - CNX Software

August 13, 2018August 13, 2018 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

Linux 4.18 Release – Main Changes, Arm and MIPS Architecture

Linus Torvalds has just announced the release of Linux 4.18: One week late(r) and here we are – 4.18 is out there. It was a very calm week, and arguably I could just have released on schedule last week, but we did have some minor updates. Mostly networking, but some vfs race fixes (mentioned in the rc8 announment as “pending”) and a couple of driver fixes (scsi, networking, i2c). Some other minor random things (arm crypto fix, parisc memory ordering fix). Shortlog appended for the (few) details. Some of these I was almost ready to just delay to until the next merge window, but they were marked for stable anyway, so it would just have caused more backporting. The vfs fixes are for old races that are really hard to hit (which is obviously why they are old and weren’t noticed earlier). Some of them _have_ been seen in real […]

June 6, 2018June 18, 2018 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Linux 4.17 Release – Main Changes, Arm & MIPS Architectures

Linus Torvalds released Linux 4.17 last Sunday: So this last week was pretty calm, even if the pattern of most of the stuff coming in on a Friday made it feel less so as the weekend approached. And while I would have liked even less changes, I really didn’t get the feeling that another week would help the release in any way, so here we are, with 4.17 released. No, I didn’t call it 5.0, even though all the git object count numerology was in place for that. It will happen in the not _too_distant future, and I’m told all the release scripts on kernel.org are ready for it, but I didn’t feel there was any real reason for it. I suspect that around 4.20 – which is I run out of fingers and toes to keep track of minor releases, and thus start getting mightily confused – I’ll switch […]

May 7, 2018May 7, 2018 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

MIPS I7200 Processor Core with nanoMIPS Architecture is Designed for LTE/5G Communications & Networking SoCs

MIPS has recently unveiled the I7200 multi-threaded multi-core processor for advanced LTE/5G communications and networking SoCs, which also happens to be the first MIPS core based on the new nanoMIPS 32-bit ISA. nanoMIPS is a variable instruction length ISA consisting of 16/32/48-bit instructions and various other optimizations that enables performance in the smallest code size. MIPS I7200 core features: 32-bit nanoMIPS Instruction Set Architecture with MIPS DSP ASE optimized instruction set extensions for integer DSP and 32-bit SIMD operations Balanced, 9-stage, dual-issue pipeline with Vertical Multi-Threading (VMT) Superscalar on a single thread per cycle Zero overhead context switching – can switch threads every clock cycle Implements MIPS MT ASE – can implement up to 3 fully OS visible Virtual Processor Elements (VPEs) per core, and up to 9 lightweight thread contexts (TCs) per core, assignable to the VPEs Configurable memory subsystem Support for caches, tightly coupled ScratchPad RAM (SPRAM), or […]

April 2, 2018April 3, 2018 by Jean-Luc Aufranc (CNXSoft) - No Comments

Linux 4.16 Release – Main Changes, Arm and MIPS Architectures

Linus Torvalds has just released Linux 4.16: So the take from final week of the 4.16 release looks a lot like rc7, in that about half of it is networking. If it wasn’t for that, it would all be very small and calm. We had a number of fixes and cleanups elsewhere, but none of it made me go “uhhuh, better let this soak for another week”. And davem didn’t think the networking was a reason to delay the release, so I’m not. End result: 4.16 is out, and the merge window for 4.17 is open and I’ll start doing pull requests tomorrow. Outside of networking, most of the last week was various arch fixlets (powerpc, arm, x86, arm64), some driver fixes (mainly scsi and rdma) and misc other noise (documentation, vm, perf). The appended shortlog gives an overview of the details (again, this is only the small stuff in […]

January 30, 2018 by Jean-Luc Aufranc (CNXSoft) - 13 Comments

Linux 4.15 Release – Main Changes, Arm and MIPS Architectures

Linus Torvald has released Linux 4.15 last Sunday: After a release cycle that was unusual in so many (bad) ways, this last week was really pleasant. Quiet and small, and no last-minute panics, just small fixes for various issues. I never got a feeling that I’d need to extend things by yet another week, and 4.15 looks fine to me. Half the changes in the last week were misc driver stuff (gpu, input, networking) with the other half being a mix of networking, core kernel and arch updates (mainly x86). But all of it is tiny. So at least we had one good week. This obviously was not a pleasant release cycle, with the whole meltdown/spectre thing coming in in the middle of the cycle and not really gelling with our normal release cycle. The extra two weeks were obviously mainly due to that whole timing issue. Also, it is […]

December 15, 2017December 15, 2017 by Jean-Luc Aufranc (CNXSoft) - No Comments

Microsemi VSC7513 and VSC7514 MIPS SoCs for Ethernet Switches Get Initial Mainline Linux Support

Microsemi VSC7514 is a 10-port Gigabit Ethernet (GbE)/SMB switch supporting a combination of 1G and 2.5G Ethernet ports, and VSC7513 comes with basically the same features except it’s limited 8 ports. Both SoCs include a MIPS processor with DDR3 memory interface, and support industrial and enterprise Ethernet switching features such as VLAN and QoS processing. Microsemi VSC751x Ocelot family was unveiled in June 2016, but I only heard about them today, as Free Electrons recently added initial support for VSC7513 & VSC7514 chip into mainline Linux with the patch series available here. Microsemi VSC7514 specifications & features: CPU / Memory Interface – Integrated 500 MHz MIPS 24KEc CPU with MMU and DDR3/DDR3L SDRAM controller Ethernet Connectivity – 4x dual media copper ports, 2x 1G SGMII ports, and 2x 1G/2.5G SGMII ports Host CPU Interfaces – PCIe 1.x and NPI CPU interface Internal shared memory buffer (8 queues per port) Jumbo […]

November 13, 2017November 29, 2017 by Jean-Luc Aufranc (CNXSoft) - 7 Comments

Linux 4.14 Release – Main Changes, ARM & MIPS Architecture

Linus Torvalds has announced the release of Linux 4.14: No surprises this week, although it is probably worth pointing out how the 0day robot has been getting even better (it was very useful before, but Fengguang has been working on making it even better, and reporting the problems it has found). Sure, some of the new reports turned out to be just 0day doing things that just don’t work (ie KASAN with old gcc versions, but also doing things like loading old ISA drivers in situations that just don’t make sense – remember when you couldn’t even ask if the hardware existed or not, and just had to know), but even then it’s been all good. The appended shortlog is obviously only for the (small) haul since rc8, and it really is tiny. Not very many commits, and they are small. The biggest thing that stands out in the diffstat […]

October 24, 2017 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

AMBE+2 Vocoder Promises High Voice Quality at Low (2.0 to 9.6 Kbps) Data Rates

Opus 1.2 open source audio codec was release a few months ago with the ability to deliver low power low high-quality audio bitrate for speech with bitrates as low as 12 Kbps. Digital Voice Systems (DVSI) claims to have gone even lower thanks to their AMBE+2 vocoder (Advanced MultiBand Excitation) providing high-quality speech at data rates from 2.0 to 9.6 kilobytes per second. AMBE+2 vocoder is said to outperform the company’s previous generation AMBE+ Vocoder as well as the G.729 and G.726 vocoders, while operating at only 4.0 Kbps. The vocoder is suitable for mobile radio, secure voice, satellite communication, computer telephony, digital voice and storage applications The solution can be integrated into product either using software licensing, or through Vocoder chips, and the company lists the following key benefits: Maintains speech intelligibility and speaker recognition at rates as low as 2.0 kbps Resistant to background noise and channel bit errors […]