mips

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on Linux 4.11 Release – Main Changes, ARM & MIPS Architecture

Linux 4.11 Release – Main Changes, ARM & MIPS Architecture

Linus Torvalds has just released Linux 4.11: So after that extra week with an rc8, things were pretty calm, and I’m much happier releasing a final 4.11 now. We still had various smaller fixes the last week, but nothing that made me go “hmm..”. Shortlog appended for people who want to peruse the details, but it’s a mix all over, with about half being drivers (networking dominates, but some sound fixlets too), with the rest being some arch updates, generic networking, and filesystem (nfs[d]) fixes. But it’s all really small, which is what I like to see the last week of the release cycle. And with this, the merge window is obviously open. I already have two pull request for 4.12 in my inbox, I expect that overnight I’ll get a lot more. Linux 4.10 added Virtual GPU support, perf c2c’ tool, improved writeback management, a faster initial WiFi connection […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on Azul Systems’ Zulu Embedded is a Build of OpenJDK for ARM, MIPS, PowerPC, and x86 Compliant with Java SE standard

Azul Systems’ Zulu Embedded is a Build of OpenJDK for ARM, MIPS, PowerPC, and x86 Compliant with Java SE standard

Yesterday as I wrote about the Embedded Systems Conference 2017 schedule I came across a potentially interesting talk entitled “Building A Brain With Raspberry Pi and Zulu Embedded JVM” by Azul Systems that will explain how to build a brain emulator using a cluster of Raspberry Pi boards. I wanted to find more about it, but I have not been able to find any details about the project/demo at this stage. However, I could still learn a bit more about Zulu Embedded, which is said to be an open source Java Virtual Machine based on OpenJDK, compliant with Java SE standard, working on 32-bit & 64-bit ARM & x86, MIPS, and PowerPC, as well as  multiple operating systems. Some of the key features of Zulu Embedded include: Java Support – Java 6, 7, 8, and 9 when available Java Configurations – Headless, headful, or compact Java Compact Profiles Hardware – […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on Linux 4.10 Release – Main Changes, ARM & MIPS Architectures

Linux 4.10 Release – Main Changes, ARM & MIPS Architectures

Linus Torvalds has just released Linux 4.10: So there it is, the final 4.10 release. It’s been quiet since rc8, but we did end up fixing several small issues, so the extra week was all good. On the whole, 4.10 didn’t end up as small as it initially looked. After the huge release that was 4.9, I expected things to be pretty quiet, but it ended up very much a fairly average release by modern kernel standards. So we have about 13,000 commits (not counting merges – that would be another 1200+ commits if you count those). The work is all over, obviously – the shortlog below is just the changes in the last week, since rc8. Go out and verify that it’s all good, and I’ll obviously start pulling stuff for 4.11 on Monday. Linus Linux 4.9 added Greybus staging support, improved security thanks to virtually mapped kernel stacks, […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on Baikal T1 BFK 1.6 MIPS Development Board Tested with OpenWrt

Baikal T1 BFK 1.6 MIPS Development Board Tested with OpenWrt

Baikal Electronics is a Russian fabless semiconductor company specializing in ARM and MIPS-based SoC, and we’ve already covered their Baikal T1 MIPS SoC announcement, as well as Tavolga Terminal TP-T22BT Debian 8 All-in-One Computer based on the processor. The company also have Baikal T1 BFK 1.6 development board, which does not appear to be publicly available yet, but one member of Habrahabr.ru forums got hold of one sample, and tested the OpenWrt SDK in Debian 8 host computer. First, we’ll have a look at the hardware they received. I don’t have the full specs of the board, but we’ll learn a little more below, in the meantime we can see two USB ports, Gigabit Ethernet ports, a 10GbE SFP cage, an mPCIe slot (I think), and two DB9 connector, as well as a bunch of other headers and connectors with SATA, GPIO, UART, I2C, SPI… I’ve then downloaded Baikal T1 BSP […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Linux 4.9 Release – Main Changes, ARM and MIPS Architectures

Linux 4.9 Release – Main Changes, ARM and MIPS Architectures

Linus Torvalds released Linux 4.9 on Sunday: So Linux 4.9 is out, and the merge window for 4.10 is thus open. With the extra week for 4.9, the timing for the merge window is obviously a bit awkward, and it technically closes in two weeks on Christmas Day. But that is a pure technicality, because I will certainly stop pulling on the 23rd at the latest, and if I get roped into Xmas food prep, even that date might be questionable. I could extend the merge window rather than cut it short, but I’m not going to. I suspect we all want a nice calm winter break, so if your stuff isn’t ready to be merged early, the solution is to just not merge it yet at all, and wait for 4.11. Just so you all know (I already bcc’d the main merge window suspects in a separate mailing last […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on 8Devices Rambutan Qualcomm Atheros QCA9557 / QCA9550 GbE & WiFi Modules and Development Kit Run OpenWrt

8Devices Rambutan Qualcomm Atheros QCA9557 / QCA9550 GbE & WiFi Modules and Development Kit Run OpenWrt

8Devices, a Lithuanian company specialized in the development and manufacturing of electronic equipment, is known for their Carambola and Carambola2 WiFi modules powered by Ralink and Qualcomm Atheros WiSoCs. The company has now introduced a new dual band WiFi module called Rambutan that comes in commercial and industrial temperature range through respectively Qualcomm Atheros QCA9557 & QCA9550 SoCs. Rambutan and Rambutan-I modules specifications: SoC Rambutan – Qualcomm Atheros QCA9557 MIPS processor @ 720 MHz Rambutan-I – Qualcomm Atheros QCA9550 MIPS processor @ 720 MHz System Memory – 128 MB DDR2 Storage – 128 MB Flash Connectivity WiFi – 802.11 a/b/g/n, 2.4 or 5 GHz, 2×2 MIMO, 300 Mbps data rate, 21 dB per chain output power; 2x u.FL connectors Ethernet – Atheros AR8032 10/100M Ethernet PHY 68x half holes with 2 x USB 2.0 host port 2 x serial port 1x 100 Base-T Ethernet port;  1000 Base-T Ethernet port  (SGMII […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 12 Comments on Vocore2 Lite is a $4 Linux MIPS WiFi Module based on Mediatek MT7688AN SoC (Crowdfunding)

Vocore2 Lite is a $4 Linux MIPS WiFi Module based on Mediatek MT7688AN SoC (Crowdfunding)

I’ve already written about Vocore v2 Crowdfunding campaign, where the second generation Vocore WiFi module supports audio, PoE, and ultimate dock, and price starting at $12. But there has been some development since the launch of the campaign, as the developer received request for a cheaper board, and after looking into it, has now added Vocore2 Lite WiFi module reward for only $4, or $7 once shipping included. He obviously had to make some trade-offs to bring the cost down, but the Lite board impressively still keep many of the same features. VoCore (2014) VoCore2 Lite (2016) VoCore2 (2016) Price 19.99 USD 3.99 USD 11.99 USD CPU RT5350, 360MHz MT7688AN MIPS24KEc @ 580MHz MT7628AN, 580MHz Memory 32MB SDRAM 64MB DDR2 128MB DDR2 Storage 16MB NOR 8MB NOR 16MB NOR Antenna Slot x1 x1 x2 On-Board ANTENNA √ × √ Wireless Speed ~75Mbps ~150Mbps ~300Mbps Ethernet Port x5 x1 / x5 […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

Imagination has just unveiled the successor of MIPS I6400 64-Bit Warrior Core with MIPS Warrior I-class I6500 heterogeneous CPU supporting up to 64 cluster, with up to 6 cores each (384 cores max), themselves up to 4 thread (1536 max), combining with IOCU (IO coherence units), and external IP such as PowerVR GPU or other hardware accelerators. The main features of MIPS I6400 processor are listed as follows:   Heterogeneous Inside – In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels. Heterogeneous Outside – The latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system […]

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