fpga News - Page 11 of 33 - CNX Software

February 8, 2022March 18, 2022 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

CLEAR is an open-source FPGA ASIC provided by Efabless’ chipIgnite

Open-source SoC designs are available to run on FPGA hardware, but few make it to silicon due to the costs involved. That’s why a couple of years ago the Google SkyWater PDK (process design kit) was released together with an offer to manufacture up to 100 pieces for free to selected designs in collaboration with Efabless. Efabless chipIgnite is an evolution of that offer with $9,750 being enough funds to manufacture 100 QFN or 300 WCSP parts, or alternatively 1,000 parts for $20 each ($20,000). Based on the company’s Caravel template SoC and the openFPGA generator framework, CLEAR open-source FPGA ASIC design is meant to promote and demonstrate the chipIgnite “paid IC creation” solution. You can participate by joining a group buying campaign on GroupGets to get a development board based on CLEAR for $74.99 plus shipping. CLEAR open-source FPGA ASIC features: FPGA – Small 8×8 (64) CLB eFPGA CPU […]

February 4, 2022February 4, 2022 by Jean-Luc Aufranc (CNXSoft) - 15 Comments

India goes RISC-V with VEGA processors

One of the main advantages of RISC-V architecture is that it is open, so any organization with the right skills can develop its own cores, and India’s government has taken up this opportunity with the Microprocessor Development Programme (MDP) helping develop VEGA RISC-V cores locally. Thanks to funding by the Ministry of Electronics and Information Technology (MeitY), the Centre for Development of Advanced Computing (C-DAC) managed to design five RISC-V processors ranging from a single-core 32-bit RISC-V microcontroller-class processor to a Linux capable quad-core 64-bit out-of-order processor. Key features of the five VEGA cores developed by the C-DAC: VEGA ET1031 – 32-bit single-core 3-stage in-order RV32IM processor with AHB/AXI4.bus, optional MMU, optional Debug VEGA AS1061 – 64-bit single-core 6-stage in-order RV64IMAFDC processor with 8KB D-cache, 8KB I-cache, FPU, AHB/AXI4 bus VEGA AS1161 – 64-bit single-core 16-stage pipeline out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, FPU, AHB/AXI4/ACE bus VEGA AS2161 […]

January 26, 2022September 23, 2022 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

FOSDEM 2022 schedule with embedded Linux, IoT, automotive… sessions

While typically taking place in Brussels, Belgium, FOSDEM 2022 will take place online just like FOSDEM 2021 due to COVID-19 restrictions. The good news is that it means anybody can attend it live from anywhere in the world, and makes it more like “FOSDIM”, replacing European with International, in “Free and Open Source Developers’ European Meeting”. FOSDEM 2022 will take place on February 5-6 with 637 speakers, 718 events, and 103 tracks. I’ve made my own little virtual schedule below mostly with sessions from the Embedded, Mobile and Automotive devroom, but also other devrooms including “Computer Aided Modeling and Design”, “FOSS on Mobile Devices”, “Libre-Open VLSI and FPGA”, and others. Saturday, February 5, 2022 12:30 – 13:00 – Five mysteries in Embedded Linux by Josef Holzmayr Once you start out in embedded Linux, there is a lot to do. Some things are obvious, some less so. First and foremost, […]

January 17, 2022February 28, 2022 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals

Tang Nano 9K FPGA is the third board from Sipeed based on GOWIN FPGA following the original Tang Nano board with 1K LUT and Tang Nano 4K launched last year with GW1NSR-LV4C (aka GW1NSR-4C) FPGA offering 4068 logical units and 64 Mbit PSRAM, plus an Arm Cortex-M3 hard processor. As its name implies, the new board comes with 9K LUTs, as well as 64 Mbit PSRAM, 32 Mbit Flash, a micro SD card, and video I/O (HDMI, RGB LCD connector) that makes it suitable to run Verilog HDL code emulating a PicoRV32 RISC-V soft-core with all peripherals. Tang Nano 9K FPGA board specifications: FPGA – GOWIN LittleBee GW1NR-9/GW1NR-LV9 8,640 logical units (LUTs) 6,480 flip-flop 17,280 bits shadow SRAM (SSRAM) 486 Kbit block SRAM (BSRAM) 64 Mbit PSRAM 608 Kbit user flash 2x PLL Up to 276x user I/O Storage – 32 Mbit SPI flash. MicroSD card socket Display I/F HDMI […]

November 29, 2021November 30, 2021 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

CaribouLite RPi HAT open-source SDR Raspberry Pi HAT tunes up to 6 GHz (Crowdfunding)

CaribouLite RPi HAT is an open-source dual-channel software-defined radio (SDR) Raspberry Pi HAT – or rather uHAT – that works in the sub-GHz ISM range and optionally the 30 MHz – 6 GHz range for the full version. Developed by Israel-based CaribouLabs, the micro HAT is equipped with a Lattice Semi ICE40LP1K FPGA, a Microchip AT86RF215 RF transceiver, two SMA antenna connectors, a Pmod expansion connector, and designed for any Raspberry Pi board with a 40-pin GPIO header. CaribouLite RPi HAT specifications: FPGA – Lattice Semi ICE40LP with 1.28 kLE RF Chipset – Microchip AT86RF215 Sub-GHz / 2.4GHz transceiver Qorvo’s RFFC5072 integrated Mixer IC (for full version only) Tuning Range CH1 Full version – 30 MHz – 6 GHz ISM version – 2.4 – 2.4835 GHz CH2 – Sub-1GHz Max Sampling Rate – 4 MSPS ADC/DAC Resolution – 13-bit Max RF Bandwidth – 2.5 MHz Transmit Power – up to […]

November 22, 2021November 22, 2021 by Jean-Luc Aufranc (CNXSoft) - 12 Comments

Renesas introduces sub 50 cents FPGA family with free Yosys-based development tools

Renesas has just unveiled the ForgeFPGA family of low-cost low-power FPGA’s to go for under 50 cents in (large) volumes following their acquisition of Dialog Semiconductors last August, who previously designed the GreenPAK programmable mixed-signal matrix. The company says its FPGAs consume half the power of competing FPGAs with a standby current of under 20uA, the price point will enable the use of FPGA in new markets and IoT products, and the tools will be free, at least as in beer, without any license to acquire or install. The full specifications are not available yet, but the ForgeFPGA Family will come with a maximum of 5,000 gates of logic, and the first devices ship with 1K and 2K Look Up Tables (LUTs), and as just mentioned, will operate at ultra-low power as low as 20 microamps in standby. ForgeFPGA is expected to target the same market as GreenPAK notably embedded […]

October 25, 2021October 24, 2021 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

My experience installing Libero SoC in Ubuntu and Windows 10

Libero SoC Windows Silver License ACTEL_BASESOC

A few weeks ago, I received Microchip PolarFire SoC FPGA Icicle Kit with FPGA fabric and hard RISC-V cores capable of handling Linux. I wrote “Getting Started with Yocto Linux BSP” tutorial for the board, and I had initially titled the current post “Getting Started with FPGA development using Libero SoC and Polarfire FPGA SoC”. I assumed I would write one or two paragraphs about the installation process, and then show how to work with Libero SoC Design Suite to create an FPGA bitstream. But instead, I spent countless hours trying to install the development tools. So I’ll report my experience to let readers avoid some of the pitfalls, and hopefully save time. (Failing to) Install Libero SoC v2021.v2 on Ubuntu 20.04 If we go to the download page, we’ll see Libero SoC v2021.2 for Windows and Libero SoC v2021.2 for Linux. Since my computer is running Ubuntu 20.04, I decided […]

October 2, 2021April 5, 2022 by Jean-Luc Aufranc (CNXSoft) - 22 Comments

Getting Started with the Yocto Linux BSP for Polarfire SoC FPGA Icicle Kit

Getting Started Guide PolarFire SoC FPGA Icicle Kit

Last month I received Microchip PolarFire SoC FPGA Icicle development kit that features PolarFire SoC FPGA with a Penta–core 64-bit RISC-V CPU subsystem and an FPGA with 254K LE, and booted it into the pre-installed Linux operating systems based on OpenEmbedded. Today, I’ll show how to get started with the Yocto BSP and run the EEMBC CoreMark benchmark, and I’ll check out the FPGA with Libero SoC Design Suite in a couple of weeks. Operating Systems supported by PolarFire SoC FPGA My initial idea was to focus this part of the review on Linux on RISC-V status, checking some system information, running some benchmarks (e.g. SBC-Bench), compiling the Linux kernel, and installing services like a LEMP stack (Linux, Nginx (pronounced Engine-X), MySQL, PHP) which could be used for WordPress hosting for instance. But then I looked at the operating systems supported with Microchip PolarFire SoC FPGA. There’s a Yocto Linux […]