Cologne Chip GateMate A1 is an FPGA with 20,480 logic elements best suited for lower-power applications and programmable with an open-source toolchain based on nMigen, Yosys, and other open-source tools. The A1 FPGA also comes with 1,280 Kbit block SRAM, four PLLs, a quad SPI interface up to 100 MHz, a 5Gbps SerDes interface, and the company offers an evaluation board to get started with development. GateMate A1 specifications: CPE Architecture 20,480 programmable elements (CPE) for combinatorial and sequential logic 40,960 Latches / Flip-Flops within programmable elements CPE consists of LUT-tree with 8 inputs Each CPE is configurable as a 2-bit full-adder or 2×2-bit multipliers Features 4x programmable PLLs quad SPI interface up to 100 MHz 1,280 Kbit dual-ported block RAM with variable data widths in 32 x 40 Kbit RAM cells Multipliers with arbitrary size implementable in CPE array Multiple clocking schemas All 162 GPIOs are configurable as single-ended […]
Cologne GateMate A1 FPGA chip with 20,480 LE is programmable with an open-source toolchain
