Author: Samrudhi Jagdale

Samrudhi is an analyst at Wired and Wireless Technologies (WAWT). With a passion for IoT, electronics, and power electronics, Samrudhi has been involved in writing engaging technical content for about 2 years.
Posted on by Samrudhi Jagdale - No Comments on Synaptics Astra SR series Arm Cortex-M55 MCUs feature Arm Ethos-U55 NPU, low-power Cortex-M4 core with microNPU

Synaptics Astra SR series Arm Cortex-M55 MCUs feature Arm Ethos-U55 NPU, low-power Cortex-M4 core with microNPU

astra sr series featured image

Synaptics unveiled an extension to its Astra Native AI platform with the new SR series of MCUs. This new product family, unlike the Astra SL series released last year, isn’t comprised of Linux-capable application processors. Instead, the Arm Cortex-M55 microcontrollers focus on providing high-performance, AI-native processing for Edge AI applications leveraging a built-in Arm Ethos-U55 NPU. Built on the Arm Cortex-M55 core and the Arm Ethos-U55 neural processing unit (NPU), these MCUs are optimized for multimodal applications, including vision, audio, and voice processing. As indicated in the MCU’s block diagram (see below), the SR series also features an optional low processing SoC unit featuring an Arm Cortex-M4 @ 100MHz and a Synaptics micro NPU engine. Such a provision in this MCU is what allows the three operation tiers the company offers with the MCU series: performance, efficiency, and ultra-low-power modes, allowing intelligence across various power levels. The MCU can switch […]

Posted on by Samrudhi Jagdale - No Comments on MIPS P8700 out-of-order 64-bit RISC-V processor targets automotive applications

MIPS P8700 out-of-order 64-bit RISC-V processor targets automotive applications

MIPS P8700 series featured Image

MIPS first unveiled the MIPS P8700 series IP along with the I8500 multiprocessor IP cores in 2022, and the company has now announced the general availability of the P8700 64-bit RISC-V core. Built for Advanced Driver Assistance Systems (ADAS), ML, and software-based automotive applications, the MIPS P8700 Multiprocessing System (MPS) scales up to 64 heterogeneous clusters of out-of-order, multi-threaded multi-core MIPS CPUs. P8700 series RISC-V processor’s RISC-V architecture The P8700 is MIPS’ first RISC-V IP. It implements the RISC-V RV64GCZba_Zbb instruction set architecture. It allows the MPS to execute atomic operations, single-precision, and double-precision floating-point operations and incorporates bit manipulation extensions, which streamline data processing tasks. This capability with compressed instructions through the RISC-V C extension (RVC) allows for out-of-order multi-threading.  P8700 series’ out-of-order multi-threading and heterogeneous clustering Out-of-order multi-threading simply means that the MPS processes multiple instructions simultaneously without following an order. Hence, the MPS can process even co-dependent […]

UP 7000 x86 SBC