Intel Agilex SoC FPGA Features Four Arm Cortex-A53 Cores

Intel announced their new Agilex FPGA family manufactured with a  10nm process earlier this April, but it only caught my eyes recently when I saw “Agilex SoC FPGA” listed in Linux 5.2 Arm’s changelog. The Intel SoC FPGA is there simply because it comes with four Arm Cortex-A53 cores.

Three family have been announced so far, although the later is shown as coming soon:

• Intel Agilex F-Series FPGAs and SoCs – Transceiver support up to 58 Gbps, increased DSP capabilities, high system integration, and 2nd Gen Intel Hyperflex architecture for a wide range of applications in Data Center, Networking, and Edge. Option to integrate the quad-core Arm Cortex-A53 processor.
• Intel Agilex I-Series SoC FPGAs – Optimized for high performance processor interface and bandwidth intensive applications. Coherent attach to Intel Xeon processors with Compute Express Link, hardened PCIe Gen 5 support and transceiver support up to 112 Gbps.
• Intel Agilex M-Series SoC FPGAs – Optimized for compute and memory intensive applications. Coherent attach to Intel Xeon processors, HBM integration, hardened DDR5 controller, and Intel Optane DC persistent memory support

The Intel Agilex F-series SoC FPGA has currently 7 SKUs that shared the following key features:

• Hard processor system – Quad-core 64-bit Arm Cortex*-A53 up to 1.5 GHz with 32 KB I/D cache, NEON coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, 2x USB 2.0, 3x Gigabit EMAC, 2x UART x2, 4x SPI, 5x I2C, 7x general purpose timers, 4x watchdog timers
• Memory devices supported – DDR4, QDR IV, RLDRAM 3
• FPGA
  • 392,000 to 2,692,760 Logic Elements
  • Optional 36Mbit eSRAM memory block
  • M20K memory blocks – 1,900 to 13,272 (259 Mbit)
  • MLAB memory count – 6,644 to 45,640 (29.2 Mbit)
  • 1.7 to 11.8 TFLOPS (single-precision)
• Up to 58 Gbps transceiver
• 1x F-Tile and optional 1x P-Tile PCIe hard IP blocks (Gen4x16 ) or bifurcateable 2X PCIe Gen4 x8 (EP) or 4X Gen4 x4 (RP)
• 2x to 4x F-Tile 10/25/50/100/200/400G Ethernet MAC + FEC hard intellectual property (IP)

You’ll find the full comparison from AGF 004 to AGF 027 in the product table.

The Intel Agilex I-series SoC FPGA currently has only 2 SKUs (AGI 022, AGI 027) with the following highlights:

• Hard processor system – Quad-core 64-bit Arm Cortex*-A53 up to 1.5 GHz with 32 KB I/D cache, NEON coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, 2x USB 2.0, 3x Gigabit EMAC, 2x UART x2, 4x SPI, 5x I2C, 7x general purpose timers, 4x watchdog timers
• Memory devices supported – DDR4, QDR IV, RLDRAM 3
• FPGA
  • 2,200,00 or 2,692,7 Logic Elements
  • M20K memory blocks – 11,616 or 13,272 (259 Mbit)
  • MLAB memory count – 32,788 or 45,640 (29.2 Mbit)
  • 9.4 to 11.8 TFLOPS (single-precision)
• Up to 112 Gbps transceiver
• 3x F-Tile PCIe hard IP blocks (Gen4x16 ) or bifurcateable 2X PCIe Gen4 x8 (EP) or 4X Gen4 x4 (RP)
• 3x R-Tile PCIe hard IP blocks (Gen5x16 ) or bifurcateable 2X PCIe Gen5 x8 (EP) or 4X Gen5 x4 (RP)
• 2x F-Tile 10/25/50/100/200/400G Ethernet

Again you’ll find the detailed comparison between AGI 022 and AGI 027 in the product matrix.

There aren’t any details about the M-series at this stage. For a comparison between Intel Agilex and Intel (Altera) earlier’s Stratix FPGAs check out section 1.4 of the device overview.

AFAICT there aren’t any development kits yet with device availability expected for Q3 2019. More details may be found on the product page.

Jean-Luc Aufranc (CNXSoft)

Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.

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